target/arm: Change gen_*set_pc_im to gen_*update_pc
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values by passing in pc difference. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221020030641.2066807-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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168122419e
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c44c8b8b99
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@ -40,7 +40,7 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop);
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TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs);
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void gen_set_cpsr(TCGv_i32 var, uint32_t mask);
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void gen_set_condexec(DisasContext *s);
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void gen_set_pc_im(DisasContext *s, target_ulong val);
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void gen_update_pc(DisasContext *s, target_long diff);
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void gen_lookup_tb(DisasContext *s);
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long vfp_reg_offset(bool dp, unsigned reg);
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long neon_full_reg_offset(unsigned reg);
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@ -140,9 +140,9 @@ static void reset_btype(DisasContext *s)
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}
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}
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void gen_a64_set_pc_im(uint64_t val)
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void gen_a64_update_pc(DisasContext *s, target_long diff)
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{
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tcg_gen_movi_i64(cpu_pc, val);
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tcg_gen_movi_i64(cpu_pc, s->pc_curr + diff);
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}
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/*
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@ -334,14 +334,14 @@ static void gen_exception_internal(int excp)
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static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
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{
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gen_a64_set_pc_im(pc);
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gen_a64_update_pc(s, pc - s->pc_curr);
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gen_exception_internal(excp);
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s->base.is_jmp = DISAS_NORETURN;
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}
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static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
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{
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_update_pc(s, 0);
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gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome));
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s->base.is_jmp = DISAS_NORETURN;
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}
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@ -376,11 +376,11 @@ static void gen_goto_tb(DisasContext *s, int n, int64_t diff)
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if (use_goto_tb(s, dest)) {
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tcg_gen_goto_tb(n);
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gen_a64_set_pc_im(dest);
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gen_a64_update_pc(s, diff);
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tcg_gen_exit_tb(s->base.tb, n);
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s->base.is_jmp = DISAS_NORETURN;
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} else {
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gen_a64_set_pc_im(dest);
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gen_a64_update_pc(s, diff);
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if (s->ss_active) {
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gen_step_complete_exception(s);
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} else {
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@ -1952,7 +1952,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
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uint32_t syndrome;
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syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_update_pc(s, 0);
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gen_helper_access_check_cp_reg(cpu_env,
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tcg_constant_ptr(ri),
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tcg_constant_i32(syndrome),
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@ -1962,7 +1962,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
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* The readfn or writefn might raise an exception;
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* synchronize the CPU state in case it does.
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*/
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_update_pc(s, 0);
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}
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/* Handle special cases first */
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@ -2172,7 +2172,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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/* The pre HVC helper handles cases when HVC gets trapped
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* as an undefined insn by runtime configuration.
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*/
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_update_pc(s, 0);
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gen_helper_pre_hvc(cpu_env);
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gen_ss_advance(s);
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gen_exception_insn_el(s, s->base.pc_next, EXCP_HVC,
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@ -2183,7 +2183,7 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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unallocated_encoding(s);
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break;
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}
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gen_a64_set_pc_im(s->pc_curr);
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gen_a64_update_pc(s, 0);
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16)));
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gen_ss_advance(s);
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gen_exception_insn_el(s, s->base.pc_next, EXCP_SMC,
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@ -14935,7 +14935,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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*/
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switch (dc->base.is_jmp) {
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default:
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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/* fall through */
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case DISAS_EXIT:
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case DISAS_JUMP:
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@ -14952,13 +14952,13 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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break;
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default:
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case DISAS_UPDATE_EXIT:
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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/* fall through */
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case DISAS_EXIT:
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tcg_gen_exit_tb(NULL, 0);
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break;
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case DISAS_UPDATE_NOCHAIN:
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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/* fall through */
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case DISAS_JUMP:
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tcg_gen_lookup_and_goto_ptr();
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@ -14967,11 +14967,11 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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case DISAS_SWI:
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break;
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case DISAS_WFE:
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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gen_helper_wfe(cpu_env);
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break;
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case DISAS_YIELD:
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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gen_helper_yield(cpu_env);
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break;
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case DISAS_WFI:
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@ -14979,7 +14979,7 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
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* This is a special case because we don't want to just halt
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* the CPU if trying to debug across a WFI.
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*/
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gen_a64_set_pc_im(dc->base.pc_next);
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gen_a64_update_pc(dc, 4);
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gen_helper_wfi(cpu_env, tcg_constant_i32(4));
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/*
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* The helper doesn't necessarily throw an exception, but we
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@ -856,7 +856,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
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case ARM_VFP_FPSID:
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if (s->current_el == 1) {
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_check_hcr_el2_trap(cpu_env,
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tcg_constant_i32(a->rt),
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tcg_constant_i32(a->reg));
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@ -768,9 +768,9 @@ void gen_set_condexec(DisasContext *s)
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}
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}
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void gen_set_pc_im(DisasContext *s, target_ulong val)
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void gen_update_pc(DisasContext *s, target_long diff)
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{
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tcg_gen_movi_i32(cpu_R[15], val);
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tcg_gen_movi_i32(cpu_R[15], s->pc_curr + diff);
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}
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/* Set PC and Thumb state from var. var is marked as dead. */
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@ -862,7 +862,7 @@ static inline void gen_bxns(DisasContext *s, int rm)
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/* The bxns helper may raise an EXCEPTION_EXIT exception, so in theory
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* we need to sync state before calling it, but:
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* - we don't need to do gen_set_pc_im() because the bxns helper will
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* - we don't need to do gen_update_pc() because the bxns helper will
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* always set the PC itself
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* - we don't need to do gen_set_condexec() because BXNS is UNPREDICTABLE
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* unless it's outside an IT block or the last insn in an IT block,
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@ -883,7 +883,7 @@ static inline void gen_blxns(DisasContext *s, int rm)
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* We do however need to set the PC, because the blxns helper reads it.
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* The blxns helper may throw an exception.
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*/
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
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gen_helper_v7m_blxns(cpu_env, var);
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tcg_temp_free_i32(var);
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s->base.is_jmp = DISAS_EXIT;
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@ -1051,7 +1051,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
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* as an undefined insn by runtime configuration (ie before
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* the insn really executes).
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*/
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_pre_hvc(cpu_env);
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/* Otherwise we will treat this as a real exception which
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* happens after execution of the insn. (The distinction matters
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@ -1059,7 +1059,7 @@ static inline void gen_hvc(DisasContext *s, int imm16)
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* for single stepping.)
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*/
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s->svc_imm = imm16;
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_HVC;
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}
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@ -1068,16 +1068,16 @@ static inline void gen_smc(DisasContext *s)
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/* As with HVC, we may take an exception either before or after
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* the insn executes.
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*/
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc()));
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_SMC;
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}
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static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
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{
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gen_set_condexec(s);
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gen_set_pc_im(s, pc);
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gen_update_pc(s, pc - s->pc_curr);
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gen_exception_internal(excp);
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s->base.is_jmp = DISAS_NORETURN;
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}
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@ -1103,10 +1103,10 @@ static void gen_exception_insn_el_v(DisasContext *s, uint64_t pc, int excp,
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uint32_t syn, TCGv_i32 tcg_el)
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{
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if (s->aarch64) {
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gen_a64_set_pc_im(pc);
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gen_a64_update_pc(s, pc - s->pc_curr);
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} else {
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gen_set_condexec(s);
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gen_set_pc_im(s, pc);
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gen_update_pc(s, pc - s->pc_curr);
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}
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gen_exception_el_v(excp, syn, tcg_el);
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s->base.is_jmp = DISAS_NORETURN;
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@ -1121,10 +1121,10 @@ void gen_exception_insn_el(DisasContext *s, uint64_t pc, int excp,
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void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
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{
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if (s->aarch64) {
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gen_a64_set_pc_im(pc);
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gen_a64_update_pc(s, pc - s->pc_curr);
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} else {
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gen_set_condexec(s);
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gen_set_pc_im(s, pc);
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gen_update_pc(s, pc - s->pc_curr);
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}
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gen_exception(excp, syn);
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s->base.is_jmp = DISAS_NORETURN;
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@ -1133,7 +1133,7 @@ void gen_exception_insn(DisasContext *s, uint64_t pc, int excp, uint32_t syn)
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static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
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{
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn));
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s->base.is_jmp = DISAS_NORETURN;
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}
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@ -2596,10 +2596,10 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
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if (translator_use_goto_tb(&s->base, dest)) {
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tcg_gen_goto_tb(n);
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gen_set_pc_im(s, dest);
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gen_update_pc(s, diff);
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tcg_gen_exit_tb(s->base.tb, n);
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} else {
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gen_set_pc_im(s, dest);
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gen_update_pc(s, diff);
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gen_goto_ptr();
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}
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s->base.is_jmp = DISAS_NORETURN;
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@ -2608,9 +2608,11 @@ static void gen_goto_tb(DisasContext *s, int n, int diff)
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/* Jump, specifying which TB number to use if we gen_goto_tb() */
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static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
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{
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int diff = dest - s->pc_curr;
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if (unlikely(s->ss_active)) {
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/* An indirect jump so that we still trigger the debug exception. */
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gen_set_pc_im(s, dest);
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gen_update_pc(s, diff);
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s->base.is_jmp = DISAS_JUMP;
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return;
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}
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@ -2627,7 +2629,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
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* gen_jmp();
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* on the second call to gen_jmp().
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*/
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gen_goto_tb(s, tbno, dest - s->pc_curr);
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gen_goto_tb(s, tbno, diff);
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break;
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case DISAS_UPDATE_NOCHAIN:
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case DISAS_UPDATE_EXIT:
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@ -2636,7 +2638,7 @@ static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
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* Avoid using goto_tb so we really do exit back to the main loop
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* and don't chain to another TB.
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*/
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gen_set_pc_im(s, dest);
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gen_update_pc(s, diff);
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gen_goto_ptr();
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s->base.is_jmp = DISAS_NORETURN;
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break;
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@ -2904,7 +2906,7 @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
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/* Sync state because msr_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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tcg_reg = load_reg(s, rn);
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gen_helper_msr_banked(cpu_env, tcg_reg,
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tcg_constant_i32(tgtmode),
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@ -2924,7 +2926,7 @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
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/* Sync state because mrs_banked() can raise exceptions */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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tcg_reg = tcg_temp_new_i32();
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gen_helper_mrs_banked(tcg_reg, cpu_env,
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tcg_constant_i32(tgtmode),
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@ -4745,7 +4747,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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}
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_access_check_cp_reg(cpu_env,
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tcg_constant_ptr(ri),
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tcg_constant_i32(syndrome),
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@ -4756,7 +4758,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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* synchronize the CPU state in case it does.
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*/
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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}
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/* Handle special cases first */
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@ -4770,7 +4772,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64,
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unallocated_encoding(s);
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return;
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}
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_WFI;
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return;
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default:
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@ -5157,7 +5159,7 @@ static void gen_srs(DisasContext *s,
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addr = tcg_temp_new_i32();
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/* get_r13_banked() will raise an exception if called from System mode */
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gen_set_condexec(s);
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gen_set_pc_im(s, s->pc_curr);
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gen_update_pc(s, 0);
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gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
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switch (amode) {
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case 0: /* DA */
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@ -6226,7 +6228,7 @@ static bool trans_YIELD(DisasContext *s, arg_YIELD *a)
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* scheduling of other vCPUs.
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*/
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
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s->base.is_jmp = DISAS_YIELD;
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}
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return true;
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@ -6242,7 +6244,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
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* implemented so we can't sleep like WFI does.
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*/
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if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
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gen_set_pc_im(s, s->base.pc_next);
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gen_update_pc(s, curr_insn_len(s));
|
||||
s->base.is_jmp = DISAS_WFE;
|
||||
}
|
||||
return true;
|
||||
|
@ -6251,7 +6253,7 @@ static bool trans_WFE(DisasContext *s, arg_WFE *a)
|
|||
static bool trans_WFI(DisasContext *s, arg_WFI *a)
|
||||
{
|
||||
/* For WFI, halt the vCPU until an IRQ. */
|
||||
gen_set_pc_im(s, s->base.pc_next);
|
||||
gen_update_pc(s, curr_insn_len(s));
|
||||
s->base.is_jmp = DISAS_WFI;
|
||||
return true;
|
||||
}
|
||||
|
@ -8761,7 +8763,7 @@ static bool trans_SVC(DisasContext *s, arg_SVC *a)
|
|||
(a->imm == semihost_imm)) {
|
||||
gen_exception_internal_insn(s, s->pc_curr, EXCP_SEMIHOST);
|
||||
} else {
|
||||
gen_set_pc_im(s, s->base.pc_next);
|
||||
gen_update_pc(s, curr_insn_len(s));
|
||||
s->svc_imm = a->imm;
|
||||
s->base.is_jmp = DISAS_SWI;
|
||||
}
|
||||
|
@ -9774,7 +9776,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|||
case DISAS_TOO_MANY:
|
||||
case DISAS_UPDATE_EXIT:
|
||||
case DISAS_UPDATE_NOCHAIN:
|
||||
gen_set_pc_im(dc, dc->base.pc_next);
|
||||
gen_update_pc(dc, curr_insn_len(dc));
|
||||
/* fall through */
|
||||
default:
|
||||
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
|
||||
|
@ -9798,13 +9800,13 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|||
gen_goto_tb(dc, 1, curr_insn_len(dc));
|
||||
break;
|
||||
case DISAS_UPDATE_NOCHAIN:
|
||||
gen_set_pc_im(dc, dc->base.pc_next);
|
||||
gen_update_pc(dc, curr_insn_len(dc));
|
||||
/* fall through */
|
||||
case DISAS_JUMP:
|
||||
gen_goto_ptr();
|
||||
break;
|
||||
case DISAS_UPDATE_EXIT:
|
||||
gen_set_pc_im(dc, dc->base.pc_next);
|
||||
gen_update_pc(dc, curr_insn_len(dc));
|
||||
/* fall through */
|
||||
default:
|
||||
/* indicate that the hash table must be used to find the next TB */
|
||||
|
@ -9844,7 +9846,7 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
|
|||
gen_set_label(dc->condlabel);
|
||||
gen_set_condexec(dc);
|
||||
if (unlikely(dc->ss_active)) {
|
||||
gen_set_pc_im(dc, dc->base.pc_next);
|
||||
gen_update_pc(dc, curr_insn_len(dc));
|
||||
gen_singlestep_exception(dc);
|
||||
} else {
|
||||
gen_goto_tb(dc, 1, curr_insn_len(dc));
|
||||
|
|
|
@ -254,7 +254,7 @@ static inline int curr_insn_len(DisasContext *s)
|
|||
* For instructions which want an immediate exit to the main loop, as opposed
|
||||
* to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
|
||||
* doesn't write the PC on exiting the translation loop so you need to ensure
|
||||
* something (gen_a64_set_pc_im or runtime helper) has done so before we reach
|
||||
* something (gen_a64_update_pc or runtime helper) has done so before we reach
|
||||
* return from cpu_tb_exec.
|
||||
*/
|
||||
#define DISAS_EXIT DISAS_TARGET_9
|
||||
|
@ -263,14 +263,14 @@ static inline int curr_insn_len(DisasContext *s)
|
|||
|
||||
#ifdef TARGET_AARCH64
|
||||
void a64_translate_init(void);
|
||||
void gen_a64_set_pc_im(uint64_t val);
|
||||
void gen_a64_update_pc(DisasContext *s, target_long diff);
|
||||
extern const TranslatorOps aarch64_translator_ops;
|
||||
#else
|
||||
static inline void a64_translate_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
static inline void gen_a64_set_pc_im(uint64_t val)
|
||||
static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue