tcg: Add atomic helpers
Add all of cmpxchg, op_fetch, fetch_op, and xchg. Handle both endian-ness, and sizes up to 8. Handle expanding non-atomically, when emulating in serial. Reviewed-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
c86c6e4c80
commit
c482cb117c
@ -89,7 +89,7 @@ endif
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#######################################################################
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# Target-independent parts used in system and user emulation
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common-obj-y += tcg-runtime.o cpus-common.o
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common-obj-y += cpus-common.o
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common-obj-y += hw/
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common-obj-y += qom/
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common-obj-y += disas/
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@ -94,6 +94,7 @@ obj-$(CONFIG_TCG_INTERPRETER) += disas/tci.o
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obj-y += fpu/softfloat.o
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obj-y += target-$(TARGET_BASE_ARCH)/
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obj-y += disas.o
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obj-y += tcg-runtime.o
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obj-$(call notempty,$(TARGET_XML_FILES)) += gdbstub-xml.o
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obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
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177
atomic_template.h
Normal file
177
atomic_template.h
Normal file
@ -0,0 +1,177 @@
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/*
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* Atomic helper templates
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* Included from tcg-runtime.c and cputlb.c.
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*
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* Copyright (c) 2016 Red Hat, Inc
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#if DATA_SIZE == 8
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# define SUFFIX q
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# define DATA_TYPE uint64_t
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# define BSWAP bswap64
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#elif DATA_SIZE == 4
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# define SUFFIX l
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# define DATA_TYPE uint32_t
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# define BSWAP bswap32
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#elif DATA_SIZE == 2
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# define SUFFIX w
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# define DATA_TYPE uint16_t
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# define BSWAP bswap16
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#elif DATA_SIZE == 1
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# define SUFFIX b
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# define DATA_TYPE uint8_t
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# define BSWAP
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#else
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# error unsupported data size
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#endif
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#if DATA_SIZE >= 4
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# define ABI_TYPE DATA_TYPE
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#else
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# define ABI_TYPE uint32_t
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#endif
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/* Define host-endian atomic operations. Note that END is used within
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the ATOMIC_NAME macro, and redefined below. */
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#if DATA_SIZE == 1
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# define END
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#elif defined(HOST_WORDS_BIGENDIAN)
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# define END _be
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#else
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# define END _le
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#endif
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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return atomic_cmpxchg__nocheck(haddr, cmpv, newv);
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}
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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return atomic_xchg__nocheck(haddr, val);
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}
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val EXTRA_ARGS) \
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{ \
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
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return atomic_##X(haddr, val); \
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} \
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GEN_ATOMIC_HELPER(fetch_add)
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GEN_ATOMIC_HELPER(fetch_and)
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GEN_ATOMIC_HELPER(fetch_or)
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GEN_ATOMIC_HELPER(fetch_xor)
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GEN_ATOMIC_HELPER(add_fetch)
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GEN_ATOMIC_HELPER(and_fetch)
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GEN_ATOMIC_HELPER(or_fetch)
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GEN_ATOMIC_HELPER(xor_fetch)
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#undef GEN_ATOMIC_HELPER
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#undef END
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#if DATA_SIZE > 1
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/* Define reverse-host-endian atomic operations. Note that END is used
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within the ATOMIC_NAME macro. */
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#ifdef HOST_WORDS_BIGENDIAN
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# define END _le
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#else
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# define END _be
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#endif
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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return BSWAP(atomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)));
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}
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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return BSWAP(atomic_xchg__nocheck(haddr, BSWAP(val)));
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}
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val EXTRA_ARGS) \
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{ \
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \
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return BSWAP(atomic_##X(haddr, BSWAP(val))); \
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}
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GEN_ATOMIC_HELPER(fetch_and)
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GEN_ATOMIC_HELPER(fetch_or)
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GEN_ATOMIC_HELPER(fetch_xor)
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GEN_ATOMIC_HELPER(and_fetch)
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GEN_ATOMIC_HELPER(or_fetch)
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GEN_ATOMIC_HELPER(xor_fetch)
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#undef GEN_ATOMIC_HELPER
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/* Note that for addition, we need to use a separate cmpxchg loop instead
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of bswaps for the reverse-host-endian helpers. */
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ABI_TYPE ATOMIC_NAME(fetch_add)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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DATA_TYPE ldo, ldn, ret, sto;
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ldo = atomic_read__nocheck(haddr);
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while (1) {
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ret = BSWAP(ldo);
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sto = BSWAP(ret + val);
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ldn = atomic_cmpxchg__nocheck(haddr, ldo, sto);
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if (ldn == ldo) {
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return ret;
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}
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ldo = ldn;
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}
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}
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ABI_TYPE ATOMIC_NAME(add_fetch)(CPUArchState *env, target_ulong addr,
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ABI_TYPE val EXTRA_ARGS)
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{
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DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP;
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DATA_TYPE ldo, ldn, ret, sto;
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ldo = atomic_read__nocheck(haddr);
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while (1) {
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ret = BSWAP(ldo) + val;
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sto = BSWAP(ret);
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ldn = atomic_cmpxchg__nocheck(haddr, ldo, sto);
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if (ldn == ldo) {
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return ret;
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}
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ldo = ldn;
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}
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}
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#undef END
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#endif /* DATA_SIZE > 1 */
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#undef BSWAP
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#undef ABI_TYPE
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#undef DATA_TYPE
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#undef SUFFIX
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#undef DATA_SIZE
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112
cputlb.c
112
cputlb.c
@ -23,15 +23,15 @@
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#include "exec/cpu_ldst.h"
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#include "exec/cputlb.h"
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#include "exec/memory-internal.h"
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#include "exec/ram_addr.h"
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#include "exec/exec-all.h"
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#include "tcg/tcg.h"
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#include "qemu/error-report.h"
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#include "exec/log.h"
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#include "exec/helper-proto.h"
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#include "qemu/atomic.h"
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/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
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/* #define DEBUG_TLB */
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@ -585,6 +585,69 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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}
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}
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/* Probe for a read-modify-write atomic operation. Do not allow unaligned
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* operations, or io operations to proceed. Return the host address. */
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static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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TCGMemOpIdx oi, uintptr_t retaddr)
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{
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size_t mmu_idx = get_mmuidx(oi);
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size_t index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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CPUTLBEntry *tlbe = &env->tlb_table[mmu_idx][index];
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target_ulong tlb_addr = tlbe->addr_write;
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TCGMemOp mop = get_memop(oi);
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int a_bits = get_alignment_bits(mop);
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int s_bits = mop & MO_SIZE;
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/* Adjust the given return address. */
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retaddr -= GETPC_ADJ;
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/* Enforce guest required alignment. */
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if (unlikely(a_bits > 0 && (addr & ((1 << a_bits) - 1)))) {
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/* ??? Maybe indicate atomic op to cpu_unaligned_access */
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cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
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mmu_idx, retaddr);
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}
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/* Enforce qemu required alignment. */
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if (unlikely(addr & ((1 << s_bits) - 1))) {
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/* We get here if guest alignment was not requested,
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or was not enforced by cpu_unaligned_access above.
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We might widen the access and emulate, but for now
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mark an exception and exit the cpu loop. */
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goto stop_the_world;
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}
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/* Check TLB entry and enforce page permissions. */
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if ((addr & TARGET_PAGE_MASK)
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!= (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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if (!VICTIM_TLB_HIT(addr_write, addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
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}
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tlb_addr = tlbe->addr_write;
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}
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/* Notice an IO access, or a notdirty page. */
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if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
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/* There's really nothing that can be done to
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support this apart from stop-the-world. */
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goto stop_the_world;
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}
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/* Let the guest notice RMW on a write-only page. */
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if (unlikely(tlbe->addr_read != tlb_addr)) {
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tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_LOAD, mmu_idx, retaddr);
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/* Since we don't support reads and writes to different addresses,
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and we do have the proper page loaded for write, this shouldn't
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ever return. But just in case, handle via stop-the-world. */
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goto stop_the_world;
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}
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return (void *)((uintptr_t)addr + tlbe->addend);
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stop_the_world:
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cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
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}
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#ifdef TARGET_WORDS_BIGENDIAN
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# define TGT_BE(X) (X)
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# define TGT_LE(X) BSWAP(X)
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@ -606,8 +669,51 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
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#define DATA_SIZE 8
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#include "softmmu_template.h"
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#undef MMUSUFFIX
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/* First set of helpers allows passing in of OI and RETADDR. This makes
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them callable from other helpers. */
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#define EXTRA_ARGS , TCGMemOpIdx oi, uintptr_t retaddr
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#define ATOMIC_NAME(X) \
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HELPER(glue(glue(glue(atomic_ ## X, SUFFIX), END), _mmu))
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#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, retaddr)
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#define DATA_SIZE 1
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#include "atomic_template.h"
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#define DATA_SIZE 2
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#include "atomic_template.h"
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#define DATA_SIZE 8
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#include "atomic_template.h"
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/* Second set of helpers are directly callable from TCG as helpers. */
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#undef EXTRA_ARGS
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#undef ATOMIC_NAME
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#undef ATOMIC_MMU_LOOKUP
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#define EXTRA_ARGS , TCGMemOpIdx oi
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#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
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#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, oi, GETPC())
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#define DATA_SIZE 1
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#include "atomic_template.h"
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#define DATA_SIZE 2
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#include "atomic_template.h"
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#define DATA_SIZE 8
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#include "atomic_template.h"
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/* Code access functions. */
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#undef MMUSUFFIX
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#define MMUSUFFIX _cmmu
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#undef GETPC
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#define GETPC() ((uintptr_t)0)
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@ -23,17 +23,10 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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/* This file is compiled once, and thus we can't include the standard
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"exec/helper-proto.h", which has includes that are target specific. */
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#include "exec/helper-head.h"
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#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \
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dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2));
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#include "tcg-runtime.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/cpu_ldst.h"
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#include "exec/exec-all.h"
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/* 32-bit helpers */
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@ -107,3 +100,37 @@ int64_t HELPER(mulsh_i64)(int64_t arg1, int64_t arg2)
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muls64(&l, &h, arg1, arg2);
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return h;
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}
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#ifndef CONFIG_SOFTMMU
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/* The softmmu versions of these helpers are in cputlb.c. */
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/* Do not allow unaligned operations to proceed. Return the host address. */
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static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
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int size, uintptr_t retaddr)
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{
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/* Enforce qemu required alignment. */
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if (unlikely(addr & (size - 1))) {
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cpu_loop_exit_atomic(ENV_GET_CPU(env), retaddr);
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}
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return g2h(addr);
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}
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/* Macro to call the above, with local variables from the use context. */
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#define ATOMIC_MMU_LOOKUP atomic_mmu_lookup(env, addr, DATA_SIZE, GETPC())
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#define ATOMIC_NAME(X) HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
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#define EXTRA_ARGS
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#define DATA_SIZE 1
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#include "atomic_template.h"
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#define DATA_SIZE 2
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#include "atomic_template.h"
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#define DATA_SIZE 4
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#include "atomic_template.h"
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#define DATA_SIZE 8
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#include "atomic_template.h"
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#endif /* !CONFIG_SOFTMMU */
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328
tcg/tcg-op.c
328
tcg/tcg-op.c
@ -1975,3 +1975,331 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
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addr, trace_mem_get_info(memop, 1));
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gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx);
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}
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static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, TCGMemOp opc)
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{
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switch (opc & MO_SSIZE) {
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case MO_SB:
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tcg_gen_ext8s_i32(ret, val);
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break;
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case MO_UB:
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tcg_gen_ext8u_i32(ret, val);
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break;
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case MO_SW:
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tcg_gen_ext16s_i32(ret, val);
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break;
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case MO_UW:
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tcg_gen_ext16u_i32(ret, val);
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break;
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default:
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tcg_gen_mov_i32(ret, val);
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break;
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}
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}
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static void tcg_gen_ext_i64(TCGv_i64 ret, TCGv_i64 val, TCGMemOp opc)
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{
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switch (opc & MO_SSIZE) {
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case MO_SB:
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tcg_gen_ext8s_i64(ret, val);
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break;
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case MO_UB:
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tcg_gen_ext8u_i64(ret, val);
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break;
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case MO_SW:
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tcg_gen_ext16s_i64(ret, val);
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break;
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case MO_UW:
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tcg_gen_ext16u_i64(ret, val);
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break;
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case MO_SL:
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tcg_gen_ext32s_i64(ret, val);
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break;
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case MO_UL:
|
||||
tcg_gen_ext32u_i64(ret, val);
|
||||
break;
|
||||
default:
|
||||
tcg_gen_mov_i64(ret, val);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv,
|
||||
TCGv_i32, TCGv_i32, TCGv_i32);
|
||||
typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv,
|
||||
TCGv_i64, TCGv_i64, TCGv_i32);
|
||||
typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv,
|
||||
TCGv_i32, TCGv_i32);
|
||||
typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv,
|
||||
TCGv_i64, TCGv_i32);
|
||||
#else
|
||||
typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32);
|
||||
typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i64);
|
||||
typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32);
|
||||
typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64);
|
||||
#endif
|
||||
|
||||
static void * const table_cmpxchg[16] = {
|
||||
[MO_8] = gen_helper_atomic_cmpxchgb,
|
||||
[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
|
||||
[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
|
||||
[MO_32 | MO_LE] = gen_helper_atomic_cmpxchgl_le,
|
||||
[MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be,
|
||||
[MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le,
|
||||
[MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be,
|
||||
};
|
||||
|
||||
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv,
|
||||
TCGv_i32 newv, TCGArg idx, TCGMemOp memop)
|
||||
{
|
||||
memop = tcg_canonicalize_memop(memop, 0, 0);
|
||||
|
||||
if (!parallel_cpus) {
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
TCGv_i32 t2 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE);
|
||||
|
||||
tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
|
||||
tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1);
|
||||
tcg_gen_qemu_st_i32(t2, addr, idx, memop);
|
||||
tcg_temp_free_i32(t2);
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i32(retv, t1, memop);
|
||||
} else {
|
||||
tcg_gen_mov_i32(retv, t1);
|
||||
}
|
||||
tcg_temp_free_i32(t1);
|
||||
} else {
|
||||
gen_atomic_cx_i32 gen;
|
||||
|
||||
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
{
|
||||
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
|
||||
gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi);
|
||||
tcg_temp_free_i32(oi);
|
||||
}
|
||||
#else
|
||||
gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv);
|
||||
#endif
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i32(retv, retv, memop);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv,
|
||||
TCGv_i64 newv, TCGArg idx, TCGMemOp memop)
|
||||
{
|
||||
memop = tcg_canonicalize_memop(memop, 1, 0);
|
||||
|
||||
if (!parallel_cpus) {
|
||||
TCGv_i64 t1 = tcg_temp_new_i64();
|
||||
TCGv_i64 t2 = tcg_temp_new_i64();
|
||||
|
||||
tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE);
|
||||
|
||||
tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
|
||||
tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1);
|
||||
tcg_gen_qemu_st_i64(t2, addr, idx, memop);
|
||||
tcg_temp_free_i64(t2);
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i64(retv, t1, memop);
|
||||
} else {
|
||||
tcg_gen_mov_i64(retv, t1);
|
||||
}
|
||||
tcg_temp_free_i64(t1);
|
||||
} else if ((memop & MO_SIZE) == MO_64) {
|
||||
gen_atomic_cx_i64 gen;
|
||||
|
||||
gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
{
|
||||
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop, idx));
|
||||
gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv, oi);
|
||||
tcg_temp_free_i32(oi);
|
||||
}
|
||||
#else
|
||||
gen(retv, tcg_ctx.tcg_env, addr, cmpv, newv);
|
||||
#endif
|
||||
} else {
|
||||
TCGv_i32 c32 = tcg_temp_new_i32();
|
||||
TCGv_i32 n32 = tcg_temp_new_i32();
|
||||
TCGv_i32 r32 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_extrl_i64_i32(c32, cmpv);
|
||||
tcg_gen_extrl_i64_i32(n32, newv);
|
||||
tcg_gen_atomic_cmpxchg_i32(r32, addr, c32, n32, idx, memop & ~MO_SIGN);
|
||||
tcg_temp_free_i32(c32);
|
||||
tcg_temp_free_i32(n32);
|
||||
|
||||
tcg_gen_extu_i32_i64(retv, r32);
|
||||
tcg_temp_free_i32(r32);
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i64(retv, retv, memop);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
|
||||
TCGArg idx, TCGMemOp memop, bool new_val,
|
||||
void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32))
|
||||
{
|
||||
TCGv_i32 t1 = tcg_temp_new_i32();
|
||||
TCGv_i32 t2 = tcg_temp_new_i32();
|
||||
|
||||
memop = tcg_canonicalize_memop(memop, 0, 0);
|
||||
|
||||
tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN);
|
||||
gen(t2, t1, val);
|
||||
tcg_gen_qemu_st_i32(t2, addr, idx, memop);
|
||||
|
||||
tcg_gen_ext_i32(ret, (new_val ? t2 : t1), memop);
|
||||
tcg_temp_free_i32(t1);
|
||||
tcg_temp_free_i32(t2);
|
||||
}
|
||||
|
||||
static void do_atomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val,
|
||||
TCGArg idx, TCGMemOp memop, void * const table[])
|
||||
{
|
||||
gen_atomic_op_i32 gen;
|
||||
|
||||
memop = tcg_canonicalize_memop(memop, 0, 0);
|
||||
|
||||
gen = table[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
{
|
||||
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
|
||||
gen(ret, tcg_ctx.tcg_env, addr, val, oi);
|
||||
tcg_temp_free_i32(oi);
|
||||
}
|
||||
#else
|
||||
gen(ret, tcg_ctx.tcg_env, addr, val);
|
||||
#endif
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i32(ret, ret, memop);
|
||||
}
|
||||
}
|
||||
|
||||
static void do_nonatomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
|
||||
TCGArg idx, TCGMemOp memop, bool new_val,
|
||||
void (*gen)(TCGv_i64, TCGv_i64, TCGv_i64))
|
||||
{
|
||||
TCGv_i64 t1 = tcg_temp_new_i64();
|
||||
TCGv_i64 t2 = tcg_temp_new_i64();
|
||||
|
||||
memop = tcg_canonicalize_memop(memop, 1, 0);
|
||||
|
||||
tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN);
|
||||
gen(t2, t1, val);
|
||||
tcg_gen_qemu_st_i64(t2, addr, idx, memop);
|
||||
|
||||
tcg_gen_ext_i64(ret, (new_val ? t2 : t1), memop);
|
||||
tcg_temp_free_i64(t1);
|
||||
tcg_temp_free_i64(t2);
|
||||
}
|
||||
|
||||
static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
|
||||
TCGArg idx, TCGMemOp memop, void * const table[])
|
||||
{
|
||||
memop = tcg_canonicalize_memop(memop, 1, 0);
|
||||
|
||||
if ((memop & MO_SIZE) == MO_64) {
|
||||
gen_atomic_op_i64 gen;
|
||||
|
||||
gen = table[memop & (MO_SIZE | MO_BSWAP)];
|
||||
tcg_debug_assert(gen != NULL);
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
{
|
||||
TCGv_i32 oi = tcg_const_i32(make_memop_idx(memop & ~MO_SIGN, idx));
|
||||
gen(ret, tcg_ctx.tcg_env, addr, val, oi);
|
||||
tcg_temp_free_i32(oi);
|
||||
}
|
||||
#else
|
||||
gen(ret, tcg_ctx.tcg_env, addr, val);
|
||||
#endif
|
||||
} else {
|
||||
TCGv_i32 v32 = tcg_temp_new_i32();
|
||||
TCGv_i32 r32 = tcg_temp_new_i32();
|
||||
|
||||
tcg_gen_extrl_i64_i32(v32, val);
|
||||
do_atomic_op_i32(r32, addr, v32, idx, memop & ~MO_SIGN, table);
|
||||
tcg_temp_free_i32(v32);
|
||||
|
||||
tcg_gen_extu_i32_i64(ret, r32);
|
||||
tcg_temp_free_i32(r32);
|
||||
|
||||
if (memop & MO_SIGN) {
|
||||
tcg_gen_ext_i64(ret, ret, memop);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \
|
||||
static void * const table_##NAME[16] = { \
|
||||
[MO_8] = gen_helper_atomic_##NAME##b, \
|
||||
[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
|
||||
[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \
|
||||
[MO_32 | MO_LE] = gen_helper_atomic_##NAME##l_le, \
|
||||
[MO_32 | MO_BE] = gen_helper_atomic_##NAME##l_be, \
|
||||
[MO_64 | MO_LE] = gen_helper_atomic_##NAME##q_le, \
|
||||
[MO_64 | MO_BE] = gen_helper_atomic_##NAME##q_be, \
|
||||
}; \
|
||||
void tcg_gen_atomic_##NAME##_i32 \
|
||||
(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, TCGMemOp memop) \
|
||||
{ \
|
||||
if (parallel_cpus) { \
|
||||
do_atomic_op_i32(ret, addr, val, idx, memop, table_##NAME); \
|
||||
} else { \
|
||||
do_nonatomic_op_i32(ret, addr, val, idx, memop, NEW, \
|
||||
tcg_gen_##OP##_i32); \
|
||||
} \
|
||||
} \
|
||||
void tcg_gen_atomic_##NAME##_i64 \
|
||||
(TCGv_i64 ret, TCGv addr, TCGv_i64 val, TCGArg idx, TCGMemOp memop) \
|
||||
{ \
|
||||
if (parallel_cpus) { \
|
||||
do_atomic_op_i64(ret, addr, val, idx, memop, table_##NAME); \
|
||||
} else { \
|
||||
do_nonatomic_op_i64(ret, addr, val, idx, memop, NEW, \
|
||||
tcg_gen_##OP##_i64); \
|
||||
} \
|
||||
}
|
||||
|
||||
GEN_ATOMIC_HELPER(fetch_add, add, 0)
|
||||
GEN_ATOMIC_HELPER(fetch_and, and, 0)
|
||||
GEN_ATOMIC_HELPER(fetch_or, or, 0)
|
||||
GEN_ATOMIC_HELPER(fetch_xor, xor, 0)
|
||||
|
||||
GEN_ATOMIC_HELPER(add_fetch, add, 1)
|
||||
GEN_ATOMIC_HELPER(and_fetch, and, 1)
|
||||
GEN_ATOMIC_HELPER(or_fetch, or, 1)
|
||||
GEN_ATOMIC_HELPER(xor_fetch, xor, 1)
|
||||
|
||||
static void tcg_gen_mov2_i32(TCGv_i32 r, TCGv_i32 a, TCGv_i32 b)
|
||||
{
|
||||
tcg_gen_mov_i32(r, b);
|
||||
}
|
||||
|
||||
static void tcg_gen_mov2_i64(TCGv_i64 r, TCGv_i64 a, TCGv_i64 b)
|
||||
{
|
||||
tcg_gen_mov_i64(r, b);
|
||||
}
|
||||
|
||||
GEN_ATOMIC_HELPER(xchg, mov2, 0)
|
||||
|
||||
#undef GEN_ATOMIC_HELPER
|
||||
|
||||
44
tcg/tcg-op.h
44
tcg/tcg-op.h
@ -854,6 +854,30 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
|
||||
tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
|
||||
}
|
||||
|
||||
void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
|
||||
TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
|
||||
TCGArg, TCGMemOp);
|
||||
|
||||
void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
|
||||
void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
|
||||
|
||||
#if TARGET_LONG_BITS == 64
|
||||
#define tcg_gen_movi_tl tcg_gen_movi_i64
|
||||
#define tcg_gen_mov_tl tcg_gen_mov_i64
|
||||
@ -932,6 +956,16 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
|
||||
#define tcg_gen_sub2_tl tcg_gen_sub2_i64
|
||||
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
|
||||
#define tcg_gen_muls2_tl tcg_gen_muls2_i64
|
||||
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
|
||||
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
|
||||
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
|
||||
#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
|
||||
#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
|
||||
#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
|
||||
#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
|
||||
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
|
||||
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
|
||||
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
|
||||
#else
|
||||
#define tcg_gen_movi_tl tcg_gen_movi_i32
|
||||
#define tcg_gen_mov_tl tcg_gen_mov_i32
|
||||
@ -1009,6 +1043,16 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
|
||||
#define tcg_gen_sub2_tl tcg_gen_sub2_i32
|
||||
#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
|
||||
#define tcg_gen_muls2_tl tcg_gen_muls2_i32
|
||||
#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
|
||||
#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
|
||||
#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
|
||||
#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
|
||||
#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
|
||||
#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
|
||||
#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
|
||||
#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
|
||||
#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
|
||||
#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
|
||||
#endif
|
||||
|
||||
#if UINTPTR_MAX == UINT32_MAX
|
||||
|
||||
@ -14,3 +14,78 @@ DEF_HELPER_FLAGS_2(sar_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
||||
|
||||
DEF_HELPER_FLAGS_2(mulsh_i64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
|
||||
DEF_HELPER_FLAGS_2(muluh_i64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
|
||||
|
||||
#ifdef CONFIG_SOFTMMU
|
||||
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG,
|
||||
i32, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG,
|
||||
i32, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG,
|
||||
i32, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG,
|
||||
i64, env, tl, i64, i64, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG,
|
||||
i32, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG,
|
||||
i32, env, tl, i32, i32, i32)
|
||||
DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG,
|
||||
i64, env, tl, i64, i64, i32)
|
||||
|
||||
#define GEN_ATOMIC_HELPERS(NAME) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), \
|
||||
TCG_CALL_NO_WG, i64, env, tl, i64, i32) \
|
||||
DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \
|
||||
TCG_CALL_NO_WG, i64, env, tl, i64, i32)
|
||||
|
||||
#else
|
||||
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgw_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgl_be, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgq_be, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgw_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgl_le, TCG_CALL_NO_WG, i32, env, tl, i32, i32)
|
||||
DEF_HELPER_FLAGS_4(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64)
|
||||
|
||||
#define GEN_ATOMIC_HELPERS(NAME) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), b), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_le), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), w_be), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_le), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), l_be), \
|
||||
TCG_CALL_NO_WG, i32, env, tl, i32) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_le), \
|
||||
TCG_CALL_NO_WG, i64, env, tl, i64) \
|
||||
DEF_HELPER_FLAGS_3(glue(glue(atomic_, NAME), q_be), \
|
||||
TCG_CALL_NO_WG, i64, env, tl, i64)
|
||||
|
||||
#endif /* CONFIG_SOFTMMU */
|
||||
|
||||
GEN_ATOMIC_HELPERS(fetch_add)
|
||||
GEN_ATOMIC_HELPERS(fetch_and)
|
||||
GEN_ATOMIC_HELPERS(fetch_or)
|
||||
GEN_ATOMIC_HELPERS(fetch_xor)
|
||||
|
||||
GEN_ATOMIC_HELPERS(add_fetch)
|
||||
GEN_ATOMIC_HELPERS(and_fetch)
|
||||
GEN_ATOMIC_HELPERS(or_fetch)
|
||||
GEN_ATOMIC_HELPERS(xor_fetch)
|
||||
|
||||
GEN_ATOMIC_HELPERS(xchg)
|
||||
|
||||
#undef GEN_ATOMIC_HELPERS
|
||||
|
||||
53
tcg/tcg.h
53
tcg/tcg.h
@ -1177,6 +1177,59 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
|
||||
# define helper_ret_ldq_cmmu helper_le_ldq_cmmu
|
||||
#endif
|
||||
|
||||
uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint64_t cmpv, uint64_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint32_t cmpv, uint32_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr,
|
||||
uint64_t cmpv, uint64_t newv,
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
#define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \
|
||||
TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \
|
||||
(CPUArchState *env, target_ulong addr, TYPE val, \
|
||||
TCGMemOpIdx oi, uintptr_t retaddr);
|
||||
|
||||
#define GEN_ATOMIC_HELPER_ALL(NAME) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint32_t, b) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \
|
||||
GEN_ATOMIC_HELPER(NAME, uint64_t, q_be)
|
||||
|
||||
GEN_ATOMIC_HELPER_ALL(fetch_add)
|
||||
GEN_ATOMIC_HELPER_ALL(fetch_sub)
|
||||
GEN_ATOMIC_HELPER_ALL(fetch_and)
|
||||
GEN_ATOMIC_HELPER_ALL(fetch_or)
|
||||
GEN_ATOMIC_HELPER_ALL(fetch_xor)
|
||||
|
||||
GEN_ATOMIC_HELPER_ALL(add_fetch)
|
||||
GEN_ATOMIC_HELPER_ALL(sub_fetch)
|
||||
GEN_ATOMIC_HELPER_ALL(and_fetch)
|
||||
GEN_ATOMIC_HELPER_ALL(or_fetch)
|
||||
GEN_ATOMIC_HELPER_ALL(xor_fetch)
|
||||
|
||||
GEN_ATOMIC_HELPER_ALL(xchg)
|
||||
|
||||
#undef GEN_ATOMIC_HELPER_ALL
|
||||
#undef GEN_ATOMIC_HELPER
|
||||
|
||||
#endif /* CONFIG_SOFTMMU */
|
||||
|
||||
#endif /* TCG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user