qtest: add libqos including PCI support

This includes basic PCI support for the PC platform.  Enough
abstraction should be present to support non-PC platforms too.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Message-id: 1366123521-4330-3-git-send-email-aliguori@us.ibm.com
This commit is contained in:
Anthony Liguori 2013-04-16 09:45:16 -05:00
parent 8a8fd63734
commit c4efe1cada
6 changed files with 495 additions and 2 deletions

2
configure vendored
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@ -4511,7 +4511,7 @@ if [ "$pixman" = "internal" ]; then
fi
# build tree in object directory in case the source is not in the current directory
DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos"
DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas"
DIRS="$DIRS roms/seabios roms/vgabios"
DIRS="$DIRS qapi-generated"

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@ -77,6 +77,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o
$(test-obj-y): QEMU_INCLUDES += -Itests
QEMU_CFLAGS += -I$(SRC_PATH)/tests
tests/test-x86-cpuid.o: QEMU_INCLUDES += -I$(SRC_PATH)/target-i386
@ -105,7 +106,6 @@ tests/test-qmp-commands.h tests/test-qmp-marshal.c :\
$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py
$(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@")
tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
@ -116,6 +116,9 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
libqos-obj-y = tests/libqos/pci.o
libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
tests/rtc-test$(EXESUF): tests/rtc-test.o
tests/m48t59-test$(EXESUF): tests/m48t59-test.o
tests/fdc-test$(EXESUF): tests/fdc-test.o

239
tests/libqos/pci-pc.c Normal file
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@ -0,0 +1,239 @@
/*
* libqos PCI bindings for PC
*
* Copyright IBM, Corp. 2012-2013
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "libqtest.h"
#include "libqos/pci-pc.h"
#include "hw/pci/pci_regs.h"
#include "qemu-common.h"
#include "qemu/host-utils.h"
#include <glib.h>
typedef struct QPCIBusPC
{
QPCIBus bus;
uint32_t pci_hole_start;
uint32_t pci_hole_size;
uint32_t pci_hole_alloc;
uint16_t pci_iohole_start;
uint16_t pci_iohole_size;
uint16_t pci_iohole_alloc;
} QPCIBusPC;
static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
{
uintptr_t port = (uintptr_t)addr;
uint8_t value;
if (port < 0x10000) {
value = inb(port);
} else {
memread(port, &value, sizeof(value));
}
return value;
}
static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
{
uintptr_t port = (uintptr_t)addr;
uint16_t value;
if (port < 0x10000) {
value = inw(port);
} else {
memread(port, &value, sizeof(value));
}
return value;
}
static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
{
uintptr_t port = (uintptr_t)addr;
uint32_t value;
if (port < 0x10000) {
value = inl(port);
} else {
memread(port, &value, sizeof(value));
}
return value;
}
static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
{
uintptr_t port = (uintptr_t)addr;
if (port < 0x10000) {
outb(port, value);
} else {
memwrite(port, &value, sizeof(value));
}
}
static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
{
uintptr_t port = (uintptr_t)addr;
if (port < 0x10000) {
outw(port, value);
} else {
memwrite(port, &value, sizeof(value));
}
}
static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
{
uintptr_t port = (uintptr_t)addr;
if (port < 0x10000) {
outl(port, value);
} else {
memwrite(port, &value, sizeof(value));
}
}
static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
return inb(0xcfc);
}
static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
return inw(0xcfc);
}
static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
return inl(0xcfc);
}
static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outb(0xcfc, value);
}
static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outw(0xcfc, value);
}
static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
{
outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
outl(0xcfc, value);
}
static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
{
QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
static const int bar_reg_map[] = {
PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
};
int bar_reg;
uint32_t addr;
uint64_t size;
uint32_t io_type;
g_assert(barno >= 0 && barno <= 5);
bar_reg = bar_reg_map[barno];
qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
addr = qpci_config_readl(dev, bar_reg);
io_type = addr & PCI_BASE_ADDRESS_SPACE;
if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
addr &= PCI_BASE_ADDRESS_IO_MASK;
} else {
addr &= PCI_BASE_ADDRESS_MEM_MASK;
}
size = (1ULL << ctzl(addr));
if (size == 0) {
return NULL;
}
if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
uint16_t loc;
g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
loc = s->pci_iohole_start + s->pci_iohole_alloc;
s->pci_iohole_alloc += size;
qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
return (void *)(intptr_t)loc;
} else {
uint64_t loc;
g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
loc = s->pci_hole_start + s->pci_hole_alloc;
s->pci_hole_alloc += size;
qpci_config_writel(dev, bar_reg, loc);
return (void *)(intptr_t)loc;
}
}
static void qpci_pc_iounmap(QPCIBus *bus, void *data)
{
/* FIXME */
}
QPCIBus *qpci_init_pc(void)
{
QPCIBusPC *ret;
ret = g_malloc(sizeof(*ret));
ret->bus.io_readb = qpci_pc_io_readb;
ret->bus.io_readw = qpci_pc_io_readw;
ret->bus.io_readl = qpci_pc_io_readl;
ret->bus.io_writeb = qpci_pc_io_writeb;
ret->bus.io_writew = qpci_pc_io_writew;
ret->bus.io_writel = qpci_pc_io_writel;
ret->bus.config_readb = qpci_pc_config_readb;
ret->bus.config_readw = qpci_pc_config_readw;
ret->bus.config_readl = qpci_pc_config_readl;
ret->bus.config_writeb = qpci_pc_config_writeb;
ret->bus.config_writew = qpci_pc_config_writew;
ret->bus.config_writel = qpci_pc_config_writel;
ret->bus.iomap = qpci_pc_iomap;
ret->bus.iounmap = qpci_pc_iounmap;
ret->pci_hole_start = 0xE0000000;
ret->pci_hole_size = 0x20000000;
ret->pci_hole_alloc = 0;
ret->pci_iohole_start = 0xc000;
ret->pci_iohole_size = 0x4000;
ret->pci_iohole_alloc = 0;
return &ret->bus;
}

20
tests/libqos/pci-pc.h Normal file
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@ -0,0 +1,20 @@
/*
* libqos PCI bindings for PC
*
* Copyright IBM, Corp. 2012-2013
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef LIBQOS_PCI_PC_H
#define LIBQOS_PCI_PC_H
#include "libqos/pci.h"
QPCIBus *qpci_init_pc(void);
#endif

151
tests/libqos/pci.c Normal file
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@ -0,0 +1,151 @@
/*
* libqos PCI bindings
*
* Copyright IBM, Corp. 2012-2013
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "libqos/pci.h"
#include "hw/pci/pci_regs.h"
#include <glib.h>
#include <stdio.h>
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
void (*func)(QPCIDevice *dev, int devfn, void *data),
void *data)
{
int slot;
for (slot = 0; slot < 32; slot++) {
int fn;
for (fn = 0; fn < 8; fn++) {
QPCIDevice *dev;
dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
if (!dev) {
continue;
}
if (vendor_id != -1 &&
qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
continue;
}
if (device_id != -1 &&
qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
continue;
}
func(dev, QPCI_DEVFN(slot, fn), data);
}
}
}
QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
{
QPCIDevice *dev;
dev = g_malloc0(sizeof(*dev));
dev->bus = bus;
dev->devfn = devfn;
if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
g_free(dev);
return NULL;
}
return dev;
}
void qpci_device_enable(QPCIDevice *dev)
{
uint16_t cmd;
/* FIXME -- does this need to be a bus callout? */
cmd = qpci_config_readw(dev, PCI_COMMAND);
cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
qpci_config_writew(dev, PCI_COMMAND, cmd);
}
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
{
return dev->bus->config_readb(dev->bus, dev->devfn, offset);
}
uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
{
return dev->bus->config_readw(dev->bus, dev->devfn, offset);
}
uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
{
return dev->bus->config_readl(dev->bus, dev->devfn, offset);
}
void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
{
dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
}
void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
{
dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
}
void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
{
dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
}
uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
{
return dev->bus->io_readb(dev->bus, data);
}
uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
{
return dev->bus->io_readw(dev->bus, data);
}
uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
{
return dev->bus->io_readl(dev->bus, data);
}
void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
{
dev->bus->io_writeb(dev->bus, data, value);
}
void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
{
dev->bus->io_writew(dev->bus, data, value);
}
void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
{
dev->bus->io_writel(dev->bus, data, value);
}
void *qpci_iomap(QPCIDevice *dev, int barno)
{
return dev->bus->iomap(dev->bus, dev, barno);
}
void qpci_iounmap(QPCIDevice *dev, void *data)
{
dev->bus->iounmap(dev->bus, data);
}

80
tests/libqos/pci.h Normal file
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@ -0,0 +1,80 @@
/*
* libqos PCI bindings
*
* Copyright IBM, Corp. 2012-2013
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#ifndef LIBQOS_PCI_H
#define LIBQOS_PCI_H
#include <stdint.h>
#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
typedef struct QPCIDevice QPCIDevice;
typedef struct QPCIBus QPCIBus;
struct QPCIBus
{
uint8_t (*io_readb)(QPCIBus *bus, void *addr);
uint16_t (*io_readw)(QPCIBus *bus, void *addr);
uint32_t (*io_readl)(QPCIBus *bus, void *addr);
void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
void (*config_writeb)(QPCIBus *bus, int devfn,
uint8_t offset, uint8_t value);
void (*config_writew)(QPCIBus *bus, int devfn,
uint8_t offset, uint16_t value);
void (*config_writel)(QPCIBus *bus, int devfn,
uint8_t offset, uint32_t value);
void *(*iomap)(QPCIBus *bus, QPCIDevice *dev, int barno);
void (*iounmap)(QPCIBus *bus, void *data);
};
struct QPCIDevice
{
QPCIBus *bus;
int devfn;
};
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
void (*func)(QPCIDevice *dev, int devfn, void *data),
void *data);
QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
void qpci_device_enable(QPCIDevice *dev);
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset);
void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value);
void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value);
void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
void *qpci_iomap(QPCIDevice *dev, int barno);
void qpci_iounmap(QPCIDevice *dev, void *data);
#endif