qtest: add libqos including PCI support
This includes basic PCI support for the PC platform. Enough abstraction should be present to support non-PC platforms too. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1366123521-4330-3-git-send-email-aliguori@us.ibm.com
This commit is contained in:
Anthony Liguori
parent
8a8fd63734
commit
c4efe1cada
2
configure
vendored
2
configure
vendored
@ -4511,7 +4511,7 @@ if [ "$pixman" = "internal" ]; then
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fi
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# build tree in object directory in case the source is not in the current directory
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DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
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DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos"
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DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas"
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DIRS="$DIRS roms/seabios roms/vgabios"
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DIRS="$DIRS qapi-generated"
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@ -77,6 +77,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
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test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o
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$(test-obj-y): QEMU_INCLUDES += -Itests
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QEMU_CFLAGS += -I$(SRC_PATH)/tests
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tests/test-x86-cpuid.o: QEMU_INCLUDES += -I$(SRC_PATH)/target-i386
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@ -105,7 +106,6 @@ tests/test-qmp-commands.h tests/test-qmp-marshal.c :\
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$(SRC_PATH)/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py
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$(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py $(gen-out-type) -o tests -p "test-" < $<, " GEN $@")
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tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
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tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
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tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) libqemuutil.a libqemustub.a
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@ -116,6 +116,9 @@ tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(
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tests/test-mul64$(EXESUF): tests/test-mul64.o libqemuutil.a
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libqos-obj-y = tests/libqos/pci.o
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libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o
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tests/rtc-test$(EXESUF): tests/rtc-test.o
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tests/m48t59-test$(EXESUF): tests/m48t59-test.o
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tests/fdc-test$(EXESUF): tests/fdc-test.o
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239
tests/libqos/pci-pc.c
Normal file
239
tests/libqos/pci-pc.c
Normal file
@ -0,0 +1,239 @@
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/*
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* libqos PCI bindings for PC
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqtest.h"
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#include "libqos/pci-pc.h"
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#include "hw/pci/pci_regs.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include <glib.h>
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typedef struct QPCIBusPC
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{
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QPCIBus bus;
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uint32_t pci_hole_start;
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uint32_t pci_hole_size;
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uint32_t pci_hole_alloc;
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uint16_t pci_iohole_start;
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uint16_t pci_iohole_size;
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uint16_t pci_iohole_alloc;
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} QPCIBusPC;
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static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint8_t value;
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if (port < 0x10000) {
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value = inb(port);
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} else {
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memread(port, &value, sizeof(value));
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}
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return value;
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}
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static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint16_t value;
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if (port < 0x10000) {
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value = inw(port);
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} else {
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memread(port, &value, sizeof(value));
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}
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return value;
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}
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static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint32_t value;
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if (port < 0x10000) {
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value = inl(port);
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} else {
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memread(port, &value, sizeof(value));
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}
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return value;
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}
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static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outb(port, value);
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} else {
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memwrite(port, &value, sizeof(value));
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}
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}
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static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outw(port, value);
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} else {
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memwrite(port, &value, sizeof(value));
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}
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}
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static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outl(port, value);
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} else {
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memwrite(port, &value, sizeof(value));
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}
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}
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static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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return inb(0xcfc);
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}
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static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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return inw(0xcfc);
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}
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static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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return inl(0xcfc);
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}
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static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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outb(0xcfc, value);
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}
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static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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outw(0xcfc, value);
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}
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static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
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{
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outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
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outl(0xcfc, value);
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}
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static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
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{
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QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
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static const int bar_reg_map[] = {
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PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
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PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
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};
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int bar_reg;
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uint32_t addr;
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uint64_t size;
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uint32_t io_type;
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g_assert(barno >= 0 && barno <= 5);
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bar_reg = bar_reg_map[barno];
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qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
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addr = qpci_config_readl(dev, bar_reg);
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io_type = addr & PCI_BASE_ADDRESS_SPACE;
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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addr &= PCI_BASE_ADDRESS_IO_MASK;
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} else {
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addr &= PCI_BASE_ADDRESS_MEM_MASK;
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}
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size = (1ULL << ctzl(addr));
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if (size == 0) {
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return NULL;
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}
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if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
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uint16_t loc;
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g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
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loc = s->pci_iohole_start + s->pci_iohole_alloc;
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s->pci_iohole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
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return (void *)(intptr_t)loc;
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} else {
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uint64_t loc;
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g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
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loc = s->pci_hole_start + s->pci_hole_alloc;
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s->pci_hole_alloc += size;
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qpci_config_writel(dev, bar_reg, loc);
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return (void *)(intptr_t)loc;
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}
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}
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static void qpci_pc_iounmap(QPCIBus *bus, void *data)
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{
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/* FIXME */
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}
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QPCIBus *qpci_init_pc(void)
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{
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QPCIBusPC *ret;
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ret = g_malloc(sizeof(*ret));
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ret->bus.io_readb = qpci_pc_io_readb;
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ret->bus.io_readw = qpci_pc_io_readw;
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ret->bus.io_readl = qpci_pc_io_readl;
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ret->bus.io_writeb = qpci_pc_io_writeb;
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ret->bus.io_writew = qpci_pc_io_writew;
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ret->bus.io_writel = qpci_pc_io_writel;
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ret->bus.config_readb = qpci_pc_config_readb;
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ret->bus.config_readw = qpci_pc_config_readw;
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ret->bus.config_readl = qpci_pc_config_readl;
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ret->bus.config_writeb = qpci_pc_config_writeb;
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ret->bus.config_writew = qpci_pc_config_writew;
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ret->bus.config_writel = qpci_pc_config_writel;
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ret->bus.iomap = qpci_pc_iomap;
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ret->bus.iounmap = qpci_pc_iounmap;
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ret->pci_hole_start = 0xE0000000;
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ret->pci_hole_size = 0x20000000;
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ret->pci_hole_alloc = 0;
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ret->pci_iohole_start = 0xc000;
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ret->pci_iohole_size = 0x4000;
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ret->pci_iohole_alloc = 0;
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return &ret->bus;
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}
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20
tests/libqos/pci-pc.h
Normal file
20
tests/libqos/pci-pc.h
Normal file
@ -0,0 +1,20 @@
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/*
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* libqos PCI bindings for PC
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef LIBQOS_PCI_PC_H
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#define LIBQOS_PCI_PC_H
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#include "libqos/pci.h"
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QPCIBus *qpci_init_pc(void);
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#endif
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151
tests/libqos/pci.c
Normal file
151
tests/libqos/pci.c
Normal file
@ -0,0 +1,151 @@
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/*
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* libqos PCI bindings
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*
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* Copyright IBM, Corp. 2012-2013
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*
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* Authors:
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* Anthony Liguori <aliguori@us.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "libqos/pci.h"
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#include "hw/pci/pci_regs.h"
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#include <glib.h>
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#include <stdio.h>
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void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
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void (*func)(QPCIDevice *dev, int devfn, void *data),
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void *data)
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{
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int slot;
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for (slot = 0; slot < 32; slot++) {
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int fn;
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for (fn = 0; fn < 8; fn++) {
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QPCIDevice *dev;
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dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
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if (!dev) {
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continue;
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}
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if (vendor_id != -1 &&
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qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
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continue;
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}
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if (device_id != -1 &&
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qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
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continue;
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}
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func(dev, QPCI_DEVFN(slot, fn), data);
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}
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}
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}
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QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
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{
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QPCIDevice *dev;
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dev = g_malloc0(sizeof(*dev));
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dev->bus = bus;
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dev->devfn = devfn;
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if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
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g_free(dev);
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return NULL;
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}
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return dev;
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}
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void qpci_device_enable(QPCIDevice *dev)
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{
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uint16_t cmd;
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/* FIXME -- does this need to be a bus callout? */
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cmd = qpci_config_readw(dev, PCI_COMMAND);
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cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
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qpci_config_writew(dev, PCI_COMMAND, cmd);
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}
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uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readb(dev->bus, dev->devfn, offset);
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}
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uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readw(dev->bus, dev->devfn, offset);
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}
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uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
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{
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return dev->bus->config_readl(dev->bus, dev->devfn, offset);
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}
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void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
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{
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dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
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{
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dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
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}
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void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
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{
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dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
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}
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uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readb(dev->bus, data);
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}
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uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readw(dev->bus, data);
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}
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uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readl(dev->bus, data);
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}
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void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
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{
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dev->bus->io_writeb(dev->bus, data, value);
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}
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void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
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{
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dev->bus->io_writew(dev->bus, data, value);
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}
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void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
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{
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dev->bus->io_writel(dev->bus, data, value);
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}
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void *qpci_iomap(QPCIDevice *dev, int barno)
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{
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return dev->bus->iomap(dev->bus, dev, barno);
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}
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void qpci_iounmap(QPCIDevice *dev, void *data)
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{
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dev->bus->iounmap(dev->bus, data);
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}
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80
tests/libqos/pci.h
Normal file
80
tests/libqos/pci.h
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* libqos PCI bindings
|
||||
*
|
||||
* Copyright IBM, Corp. 2012-2013
|
||||
*
|
||||
* Authors:
|
||||
* Anthony Liguori <aliguori@us.ibm.com>
|
||||
*
|
||||
* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
||||
* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef LIBQOS_PCI_H
|
||||
#define LIBQOS_PCI_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
|
||||
|
||||
typedef struct QPCIDevice QPCIDevice;
|
||||
typedef struct QPCIBus QPCIBus;
|
||||
|
||||
struct QPCIBus
|
||||
{
|
||||
uint8_t (*io_readb)(QPCIBus *bus, void *addr);
|
||||
uint16_t (*io_readw)(QPCIBus *bus, void *addr);
|
||||
uint32_t (*io_readl)(QPCIBus *bus, void *addr);
|
||||
|
||||
void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
|
||||
void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
|
||||
void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
|
||||
|
||||
uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
|
||||
uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
|
||||
uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
|
||||
|
||||
void (*config_writeb)(QPCIBus *bus, int devfn,
|
||||
uint8_t offset, uint8_t value);
|
||||
void (*config_writew)(QPCIBus *bus, int devfn,
|
||||
uint8_t offset, uint16_t value);
|
||||
void (*config_writel)(QPCIBus *bus, int devfn,
|
||||
uint8_t offset, uint32_t value);
|
||||
|
||||
void *(*iomap)(QPCIBus *bus, QPCIDevice *dev, int barno);
|
||||
void (*iounmap)(QPCIBus *bus, void *data);
|
||||
};
|
||||
|
||||
struct QPCIDevice
|
||||
{
|
||||
QPCIBus *bus;
|
||||
int devfn;
|
||||
};
|
||||
|
||||
void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
|
||||
void (*func)(QPCIDevice *dev, int devfn, void *data),
|
||||
void *data);
|
||||
QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
|
||||
|
||||
void qpci_device_enable(QPCIDevice *dev);
|
||||
|
||||
uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
|
||||
uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
|
||||
uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset);
|
||||
|
||||
void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value);
|
||||
void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value);
|
||||
void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
|
||||
|
||||
uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
|
||||
uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
|
||||
uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
|
||||
|
||||
void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
|
||||
void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
|
||||
void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
|
||||
|
||||
void *qpci_iomap(QPCIDevice *dev, int barno);
|
||||
void qpci_iounmap(QPCIDevice *dev, void *data);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user