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add Westmere as a qemu cpu model (v2)

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Version 1 of this patch was:

Message-Id: <1307041990-26194-11-git-send-email-ehabkost@redhat.com
http://marc.info/?l=qemu-devel&m=130704415919346

This version doesn't have the duplicate feature bits on extfeature_edx, though,
as they are being removed from the Intel models (as they are reserved bits on
Intel CPUs).

Version 1 patch description:

    This patch adds Westmere as a qemu cpu model.  The only
    additional guest visible feature of a Westmere relative
    to Nehalem is the inclusion of AES instructions.  However
    as other non-ABI visible modifications exist along with
    fabrication changes, the CPUID data of the corresponding
    deployed silicon was altered slightly to reflect this.

    We've seen isolated cases where apparently unrelated yet
    slightly incoherent CPUID data has caused problems, most
    notably during guest boot.  Providing Westmere as a
    model separate fro Nehalem allows us to more easily address
    such quirks.

    [ehabkost: edited commit message to have a better Subject line]

    Signed-off-by: john cooper <john.cooper@redhat.com>
    Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

Changes version 1 -> version 2:
 - Remove the duplicate feature bits on extfeature_edx, that are
   reserved on Intel CPUs
 - Reorder feature flags
 - Remove x2apic from the definition because x2apic requires some fixes
   that have to be resubmitted

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Eduardo Habkost 2012-02-17 14:41:24 -02:00 committed by Anthony Liguori
parent df07ec5626
commit c58a6694f1
1 changed files with 14 additions and 0 deletions
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14
sysconfigs/target/target-x86_64.conf
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@ -42,6 +42,20 @@
xlevel = "0x8000000A"
model_id = "Intel Core i7 9xx (Nehalem Class Core i7)"
[cpudef]
name = "Westmere"
level = "11"
vendor = "GenuineIntel"
family = "6"
model = "44"
stepping = "1"
feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu"
feature_ecx = "aes popcnt sse4.2 sse4.1 cx16 ssse3 sse3"
extfeature_edx = "i64 syscall xd"
extfeature_ecx = "lahf_lm"
xlevel = "0x8000000A"
model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)"
[cpudef]
name = "Opteron_G1"
level = "5"