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target-ppc: Add xvxsigsp instruction

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xvxsigsp: VSX Vector Extract Significand Single Precision

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Nikunj A Dadhania 2017-01-10 14:20:41 +05:30 committed by David Gibson
parent 46804e2875
commit c5969d2eb1
4 changed files with 24 additions and 0 deletions
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20
target/ppc/fpu_helper.c
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@ -3026,3 +3026,23 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_XXPERM(xxperm, 0) VSX_XXPERM(xxperm, 0)
VSX_XXPERM(xxpermr, 1) VSX_XXPERM(xxpermr, 1)
void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
{
ppc_vsr_t xt, xb;
uint32_t exp, i, fraction;
getVSR(xB(opcode), &xb, env);
memset(&xt, 0, sizeof(xt));
for (i = 0; i < 4; i++) {
exp = (xb.VsrW(i) >> 23) & 0xFF;
fraction = xb.VsrW(i) & 0x7FFFFF;
if (exp != 0 && exp != 255) {
xt.VsrW(i) = fraction | 0x00800000;
} else {
xt.VsrW(i) = fraction;
}
}
putVSR(xT(opcode), &xt, env);
}

1
target/ppc/helper.h
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@ -545,6 +545,7 @@ DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32) DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32) DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32) DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(xvxsigsp, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32) DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32) DEF_HELPER_2(efscfui, i32, env, i32)

2
target/ppc/translate/vsx-impl.inc.c
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@ -1430,6 +1430,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
tcg_gen_andi_i64(xtl, xtl, 0x7FF); tcg_gen_andi_i64(xtl, xtl, 0x7FF);
} }
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
#undef GEN_XX2FORM #undef GEN_XX2FORM
#undef GEN_XX3FORM #undef GEN_XX3FORM
#undef GEN_XX2IFORM #undef GEN_XX2IFORM

1
target/ppc/translate/vsx-ops.inc.c
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@ -128,6 +128,7 @@ GEN_XX3FORM(xviexpsp, 0x00, 0x1B, PPC2_ISA300),
GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300), GEN_XX3FORM(xviexpdp, 0x00, 0x1F, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpdp, 0x16, 0x1D, 0x00, PPC2_ISA300),
GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300), GEN_XX2FORM_EO(xvxexpsp, 0x16, 0x1D, 0x08, PPC2_ISA300),
GEN_XX2FORM_EO(xvxsigsp, 0x16, 0x1D, 0x09, PPC2_ISA300),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX), GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),