From a859595791e6ac5c14afe0b8a53634bf1cc21f0f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fran=C3=A7ois=20Baldassari?= Date: Thu, 19 Nov 2015 12:09:52 +0000 Subject: [PATCH 1/3] hw/arm_gic: Correctly restore nested irq priority MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Upon activating an interrupt, set the corresponding priority bit in the APR/NSAPR registers without touching the currently set bits. In the event of nested interrupts, the GIC will then have the information it needs to restore the priority of the pre-empted interrupt once the higher priority interrupt finishes execution. Signed-off-by: François Baldassari Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d71aeb8a2a..13e297d52e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -254,9 +254,9 @@ static void gic_activate_irq(GICState *s, int cpu, int irq) int bitno = preemption_level % 32; if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) { - s->nsapr[regno][cpu] &= (1 << bitno); + s->nsapr[regno][cpu] |= (1 << bitno); } else { - s->apr[regno][cpu] &= (1 << bitno); + s->apr[regno][cpu] |= (1 << bitno); } s->running_priority[cpu] = prio; From 43bfa4a100687af8d293fef0a197839b51400fca Mon Sep 17 00:00:00 2001 From: Sergey Fedorov Date: Tue, 17 Nov 2015 16:38:46 +0300 Subject: [PATCH 2/3] target-arm: Update condexec before CP access check in AA32 translation Coprocessor access instructions are allowed inside IT block. gen_helper_access_check_cp_reg() can raise an exceptions thus condexec bits should be updated before. Signed-off-by: Sergey Fedorov Message-id: 1447767527-21268-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 43518541e1..739f373fc2 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } + gen_set_condexec(s); gen_set_pc_im(s, s->pc - 4); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome); From ce8a1b5449cd8c4c2831abb581d3208c3a3745a0 Mon Sep 17 00:00:00 2001 From: Sergey Fedorov Date: Tue, 17 Nov 2015 16:38:47 +0300 Subject: [PATCH 3/3] target-arm: Update condexec before arch BP check in AA32 translation Architectural breakpoint check could raise an exceptions, thus condexec bits should be updated before calling gen_helper_check_breakpoints(). Signed-off-by: Sergey Fedorov Message-id: 1447767527-21268-3-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target-arm/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-arm/translate.c b/target-arm/translate.c index 739f373fc2..5d22879755 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11374,6 +11374,7 @@ void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb) QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { if (bp->pc == dc->pc) { if (bp->flags & BP_CPU) { + gen_set_condexec(dc); gen_set_pc_im(dc, dc->pc); gen_helper_check_breakpoints(cpu_env); /* End the TB early; it's likely not going to be executed */