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hw/xtensa: fix reset value of MIROUT register of MX PIC 

MX PIC comes out of reset with IRQ routing registers set to 0, thus
not delivering any external IRQ to any connected CPU by default.
Fix the model to match the hardware.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov 2022-04-26 09:24:01 -07:00
parent 9e377be1f0
commit c6f3f334d1
1 changed files with 1 additions and 1 deletions
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2
hw/xtensa/mx_pic.c
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@ -334,7 +334,7 @@ void xtensa_mx_pic_reset(void *opaque)
mx->miasg = 0;
mx->mipipart = 0;
for (i = 0; i < mx->n_irq; ++i) {
mx->mirout[i] = 1;
mx->mirout[i] = 0;
}
for (i = 0; i < mx->n_cpu; ++i) {
mx->cpu[i].mipicause = 0;