tcg/i386: Support INDEX_op_extract2_{i32,i64}
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -124,7 +124,7 @@ extern bool have_avx2;
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 1
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#define TCG_TARGET_HAS_extract2_i32 0
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#define TCG_TARGET_HAS_extract2_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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@ -163,7 +163,7 @@ extern bool have_avx2;
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_extract2_i64 0
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#define TCG_TARGET_HAS_extract2_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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#define TCG_TARGET_HAS_sub2_i64 1
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@ -452,6 +452,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define OPC_SHUFPS (0xc6 | P_EXT)
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#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
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#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
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#define OPC_SHRD_Ib (0xac | P_EXT)
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#define OPC_TESTL (0x85)
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#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
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#define OPC_UD2 (0x0b | P_EXT)
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@ -2587,6 +2588,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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break;
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OP_32_64(extract2):
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/* Note that SHRD outputs to the r/m operand. */
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tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
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tcg_out8(s, args[3]);
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break;
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case INDEX_op_mb:
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tcg_out_mb(s, a0);
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break;
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@ -2845,6 +2852,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
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static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
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static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
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static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
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static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
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static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
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static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
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@ -2970,6 +2978,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_ctpop_i32:
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case INDEX_op_ctpop_i64:
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return &r_r;
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case INDEX_op_extract2_i32:
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case INDEX_op_extract2_i64:
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return &r_0_r;
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case INDEX_op_deposit_i32:
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case INDEX_op_deposit_i64:
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