target/loongarch: Implement Chip Configuraiton Version Register(0x0000)
According to the 3A5000 manual 4.1 implement Chip Configuration Version Register(0x0000). Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>
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@ -546,6 +546,8 @@ static void loongarch_qemu_write(void *opaque, hwaddr addr,
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static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
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{
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switch (addr) {
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case VERSION_REG:
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return 0x11ULL;
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case FEATURE_REG:
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return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
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1ULL << IOCSRF_CSRIPI;
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@ -28,6 +28,7 @@
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#define IOCSRF_GMOD 9
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#define IOCSRF_VM 11
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#define VERSION_REG 0x0
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#define FEATURE_REG 0x8
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#define VENDOR_REG 0x10
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#define CPUNAME_REG 0x20
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