hw/arm/npcm7xx: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()

NPCM7XX models have been commited after the conversion from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible").
Manually convert them.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230109140306.23161-11-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2023-01-09 15:03:02 +01:00 committed by Peter Maydell
parent a91179e7a4
commit c79aa350ea
10 changed files with 26 additions and 39 deletions

View File

@ -42,7 +42,7 @@
* @iref: The internal reference voltage, initialized at launch time.
* @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
*/
typedef struct {
struct NPCM7xxADCState {
SysBusDevice parent;
MemoryRegion iomem;
@ -60,10 +60,9 @@ typedef struct {
uint32_t iref;
uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
} NPCM7xxADCState;
};
#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
#define NPCM7XX_ADC(obj) \
OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxADCState, NPCM7XX_ADC)
#endif /* NPCM7XX_ADC_H */

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@ -52,7 +52,7 @@
#define NPCM7XX_NR_PWM_MODULES 2
typedef struct NPCM7xxMachine {
struct NPCM7xxMachine {
MachineState parent;
/*
* PWM fan splitter. each splitter connects to one PWM output and
@ -60,11 +60,10 @@ typedef struct NPCM7xxMachine {
*/
SplitIRQ fan_splitter[NPCM7XX_NR_PWM_MODULES *
NPCM7XX_PWM_PER_MODULE];
} NPCM7xxMachine;
};
#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx")
#define NPCM7XX_MACHINE(obj) \
OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMachine, NPCM7XX_MACHINE)
typedef struct NPCM7xxMachineClass {
MachineClass parent;
@ -77,7 +76,7 @@ typedef struct NPCM7xxMachineClass {
#define NPCM7XX_MACHINE_GET_CLASS(obj) \
OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE)
typedef struct NPCM7xxState {
struct NPCM7xxState {
DeviceState parent;
ARMCPU cpu[NPCM7XX_MAX_NUM_CPUS];
@ -105,10 +104,10 @@ typedef struct NPCM7xxState {
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
NPCM7xxSDHCIState mmc;
} NPCM7xxState;
};
#define TYPE_NPCM7XX "npcm7xx"
#define NPCM7XX(obj) OBJECT_CHECK(NPCM7xxState, (obj), TYPE_NPCM7XX)
OBJECT_DECLARE_TYPE(NPCM7xxState, NPCM7xxClass, NPCM7XX)
#define TYPE_NPCM730 "npcm730"
#define TYPE_NPCM750 "npcm750"
@ -122,11 +121,6 @@ typedef struct NPCM7xxClass {
uint32_t num_cpus;
} NPCM7xxClass;
#define NPCM7XX_CLASS(klass) \
OBJECT_CLASS_CHECK(NPCM7xxClass, (klass), TYPE_NPCM7XX)
#define NPCM7XX_GET_CLASS(obj) \
OBJECT_GET_CLASS(NPCM7xxClass, (obj), TYPE_NPCM7XX)
/**
* npcm7xx_load_kernel - Loads memory with everything needed to boot
* @machine - The machine containing the SoC to be booted.

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@ -68,7 +68,7 @@ typedef enum NPCM7xxSMBusStatus {
* @rx_cur: The current position of rx_fifo.
* @status: The current status of the SMBus.
*/
typedef struct NPCM7xxSMBusState {
struct NPCM7xxSMBusState {
SysBusDevice parent;
MemoryRegion iomem;
@ -104,10 +104,9 @@ typedef struct NPCM7xxSMBusState {
uint8_t rx_cur;
NPCM7xxSMBusStatus status;
} NPCM7xxSMBusState;
};
#define TYPE_NPCM7XX_SMBUS "npcm7xx-smbus"
#define NPCM7XX_SMBUS(obj) OBJECT_CHECK(NPCM7xxSMBusState, (obj), \
TYPE_NPCM7XX_SMBUS)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxSMBusState, NPCM7XX_SMBUS)
#endif /* NPCM7XX_SMBUS_H */

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@ -175,6 +175,6 @@ struct NPCM7xxCLKState {
};
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxCLKState, NPCM7XX_CLK)
#endif /* NPCM7XX_CLK_H */

View File

@ -55,7 +55,7 @@
*/
#define NPCM7XX_GCR_NR_REGS (0x148 / sizeof(uint32_t))
typedef struct NPCM7xxGCRState {
struct NPCM7xxGCRState {
SysBusDevice parent;
MemoryRegion iomem;
@ -65,9 +65,9 @@ typedef struct NPCM7xxGCRState {
uint32_t reset_pwron;
uint32_t reset_mdlr;
uint32_t reset_intcr3;
} NPCM7xxGCRState;
};
#define TYPE_NPCM7XX_GCR "npcm7xx-gcr"
#define NPCM7XX_GCR(obj) OBJECT_CHECK(NPCM7xxGCRState, (obj), TYPE_NPCM7XX_GCR)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxGCRState, NPCM7XX_GCR)
#endif /* NPCM7XX_GCR_H */

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@ -49,7 +49,7 @@
* @max_rpm: The maximum rpm for fans. Order: A0, B0, A1, B1.
* @duty: The duty cycles for fans, relative to NPCM7XX_PWM_MAX_DUTY.
*/
typedef struct NPCM7xxMFTState {
struct NPCM7xxMFTState {
SysBusDevice parent;
MemoryRegion iomem;
@ -61,10 +61,9 @@ typedef struct NPCM7xxMFTState {
uint32_t max_rpm[NPCM7XX_MFT_FANIN_COUNT];
uint32_t duty[NPCM7XX_MFT_FANIN_COUNT];
} NPCM7xxMFTState;
};
#define TYPE_NPCM7XX_MFT "npcm7xx-mft"
#define NPCM7XX_MFT(obj) \
OBJECT_CHECK(NPCM7xxMFTState, (obj), TYPE_NPCM7XX_MFT)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxMFTState, NPCM7XX_MFT)
#endif /* NPCM7XX_MFT_H */

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@ -101,7 +101,6 @@ struct NPCM7xxPWMState {
};
#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
#define NPCM7XX_PWM(obj) \
OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxPWMState, NPCM7XX_PWM)
#endif /* NPCM7XX_PWM_H */

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@ -18,7 +18,7 @@
#include "hw/sysbus.h"
typedef struct NPCM7xxRNGState {
struct NPCM7xxRNGState {
SysBusDevice parent;
MemoryRegion iomem;
@ -26,9 +26,9 @@ typedef struct NPCM7xxRNGState {
uint8_t rngcs;
uint8_t rngd;
uint8_t rngmode;
} NPCM7xxRNGState;
};
#define TYPE_NPCM7XX_RNG "npcm7xx-rng"
#define NPCM7XX_RNG(obj) OBJECT_CHECK(NPCM7xxRNGState, (obj), TYPE_NPCM7XX_RNG)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxRNGState, NPCM7XX_RNG)
#endif /* NPCM7XX_RNG_H */

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@ -277,10 +277,7 @@ struct NPCM7xxEMCState {
bool rx_active;
};
typedef struct NPCM7xxEMCState NPCM7xxEMCState;
#define TYPE_NPCM7XX_EMC "npcm7xx-emc"
#define NPCM7XX_EMC(obj) \
OBJECT_CHECK(NPCM7xxEMCState, (obj), TYPE_NPCM7XX_EMC)
OBJECT_DECLARE_SIMPLE_TYPE(NPCM7xxEMCState, NPCM7XX_EMC)
#endif /* NPCM7XX_EMC_H */

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@ -51,7 +51,7 @@ typedef struct NPCM7xxRegs {
uint32_t boottoctrl;
} NPCM7xxRegisters;
typedef struct NPCM7xxSDHCIState {
struct NPCM7xxSDHCIState {
SysBusDevice parent;
MemoryRegion container;
@ -60,6 +60,6 @@ typedef struct NPCM7xxSDHCIState {
NPCM7xxRegisters regs;
SDHCIState sdhci;
} NPCM7xxSDHCIState;
};
#endif /* NPCM7XX_SDHCI_H */