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MIPS patches 2016-07-29 

Changes:
 * bug fixes
 -----BEGIN PGP SIGNATURE-----
 
 iQEcBAABAgAGBQJXmxddAAoJEFIRjjwLKdprjGgH/iVvQlFekQhD5l9ZaHM3RIhZ
 bBFpY9mu9VS3tPkmWal/+mrxsSh7Kz0lBMN0X+XA3xw31/a6E0uLXLGqDQybfBG9
 wHF4iIVSOk2cFH1l6gfKT481IGYWVzlWQO8wBHey6OicqixRUvN9modBe2nUU+IL
 s07MhhCvbBqDCBJpZ8CWlqwElH3m4NGH3B7Mgh3V4MLuFT6xiJFpKOy7QhzeqE2I
 e6Et19PqRk0Nypv3N90XC4IVeMVxlaRCETMjwwWONxPMjSLxfXMrXME5ba/ERRPU
 vNofMPpQlXFvRJ7OGFBun35h+G1JOMQSg/Uws03vwDoqFBOXd5usPCkSAahXeNk=
 =PGGJ
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160729' into staging

MIPS patches 2016-07-29

Changes:
* bug fixes

# gpg: Signature made Fri 29 Jul 2016 09:44:13 BST
# gpg:                using RSA key 0x52118E3C0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
# Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4  4FC0 5211 8E3C 0B29 DA6B

* remotes/lalrae/tags/mips-20160729:
  target-mips: fix EntryHi.EHINV being cleared on TLB exception
  hw/mips_malta: Fix YAMON API print routine

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2016-07-29 13:05:55 +01:00
parent df2c35902e 701074a6fc
commit c7e9aafe5c
2 changed files with 2 additions and 1 deletions
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2
hw/mips/mips_malta.c
View File

@ -727,7 +727,7 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x0ff0021c); /* jal 870 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x08000205); /* j 814 */
stl_p(p++, 0x1000fff9); /* b 814 */
stl_p(p++, 0x00000000); /* nop */
stl_p(p++, 0x01a00009); /* jalr t5 */
stl_p(p++, 0x01602021); /* move a0,t3 */

1
target-mips/helper.c
View File

@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
((address >> 9) & 0x007ffff0);
env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) |
(env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) |
(address & (TARGET_PAGE_MASK << 1));
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;