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target/s390x: Define TARGET_HAS_PRECISE_SMC

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PoP (Sequence of Storage References -> Instruction Fetching) says:

    ... if a store that is conceptually earlier is
    made by the same CPU using the same effective
    address as that by which the instruction is subse-
    quently fetched, the updated information is obtained ...

QEMU already has support for this in the common code; enable it for
s390x.

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-Id: <20230807114921.438881-1-iii@linux.ibm.com>
Acked-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Ilya Leoshkevich 2023-08-07 13:48:20 +02:00 committed by Thomas Huth
parent 17780edd81
commit c7f41e4f53
1 changed files with 2 additions and 0 deletions
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target/s390x/cpu.h
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@ -36,6 +36,8 @@
/* The z/Architecture has a strong memory model with some store-after-load re-ordering */
#define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
#define TARGET_HAS_PRECISE_SMC
#define TARGET_INSN_START_EXTRA_WORDS 2
#define MMU_USER_IDX 0