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target/arm: Don't add all MIDR aliases for cores that implement PMSA 

Cores with PMSA have the MPUIR register which has the
same encoding as the MIDR alias with opc2=4. So we only
add that alias if we are not realizing a core that
implements PMSA.

Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221206102504.165775-2-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Tobias Röhmel 2022-12-06 11:24:58 +01:00 committed by Peter Maydell
parent 9e65f4e6da
commit c7f786abe2
1 changed files with 9 additions and 4 deletions
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13
target/arm/helper.c
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@ -8153,10 +8153,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr, .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
.readfn = midr_read }, .readfn = midr_read },
/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */ /* crn = 0 op1 = 0 crm = 0 op2 = 7 : AArch32 aliases of MIDR */
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
.access = PL1_R, .resetvalue = cpu->midr },
{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7, .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
.access = PL1_R, .resetvalue = cpu->midr }, .access = PL1_R, .resetvalue = cpu->midr },
@ -8166,6 +8163,11 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.accessfn = access_aa64_tid1, .accessfn = access_aa64_tid1,
.type = ARM_CP_CONST, .resetvalue = cpu->revidr }, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
}; };
ARMCPRegInfo id_v8_midr_alias_cp_reginfo = {
.name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
.access = PL1_R, .resetvalue = cpu->midr
};
ARMCPRegInfo id_cp_reginfo[] = { ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */ /* These are common to v8 and pre-v8 */
{ .name = "CTR", { .name = "CTR",
@ -8231,6 +8233,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} }
if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_V8)) {
define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo); define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
if (!arm_feature(env, ARM_FEATURE_PMSA)) {
define_one_arm_cp_reg(cpu, &id_v8_midr_alias_cp_reginfo);
}
} else { } else {
define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo); define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
} }