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target/loongarch: Separate the hardware flags into MMU index and PLV

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Regarding the patchset v3 has been merged into main line, and not
approved, this patch updates to patchset v4.

Fixes: b4bda200 ("target/loongarch: Adjust the layout of hardware flags bit fields")
Link: https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg00808.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Rui Wang <wangrui@loongson.cn>
Message-Id: <20221107024526.702297-2-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
This commit is contained in:
Rui Wang 2022-11-07 10:45:25 +08:00 committed by Song Gao
parent 466e81ff12
commit c8885b8839
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GPG Key ID: 40A2FFF239263EDF
5 changed files with 18 additions and 16 deletions
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18
target/loongarch/cpu.h
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@ -374,21 +374,21 @@ struct LoongArchCPUClass {
* 0 for kernel mode, 3 for user mode.
* Define an extra index for DA(direct addressing) mode.
*/
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 3
#define MMU_DA_IDX 4
#define MMU_PLV_KERNEL 0
#define MMU_PLV_USER 3
#define MMU_IDX_KERNEL MMU_PLV_KERNEL
#define MMU_IDX_USER MMU_PLV_USER
#define MMU_IDX_DA 4
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
return MMU_IDX_USER;
#else
uint8_t pg = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG);
if (!pg) {
return MMU_DA_IDX;
if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
}
return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
return MMU_IDX_DA;
#endif
}

4
target/loongarch/insn_trans/trans_privileged.c.inc
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@ -159,7 +159,7 @@ static const CSRInfo csr_info[] = {
static bool check_plv(DisasContext *ctx)
{
if (ctx->mem_idx == MMU_USER_IDX) {
if (ctx->plv == MMU_PLV_USER) {
generate_exception(ctx, EXCCODE_IPE);
return true;
}
@ -335,7 +335,7 @@ TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d)
static void check_mmu_idx(DisasContext *ctx)
{
if (ctx->mem_idx != MMU_DA_IDX) {
if (ctx->mem_idx != MMU_IDX_DA) {
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
}

4
target/loongarch/tlb_helper.c
View File

@ -170,8 +170,8 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
{
int user_mode = mmu_idx == MMU_USER_IDX;
int kernel_mode = mmu_idx == MMU_KERNEL_IDX;
int user_mode = mmu_idx == MMU_IDX_USER;
int kernel_mode = mmu_idx == MMU_IDX_KERNEL;
uint32_t plv, base_c, base_v;
int64_t addr_high;
uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA);

5
target/loongarch/translate.c
View File

@ -75,10 +75,11 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
DisasContext *ctx = container_of(dcbase, DisasContext, base);
ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) {
ctx->mem_idx = ctx->base.tb->flags & HW_FLAGS_PLV_MASK;
ctx->mem_idx = ctx->plv;
} else {
ctx->mem_idx = MMU_DA_IDX;
ctx->mem_idx = MMU_IDX_DA;
}
/* Bound the number of insns to execute to those left on the page. */

3
target/loongarch/translate.h
View File

@ -29,7 +29,8 @@ typedef struct DisasContext {
DisasContextBase base;
target_ulong page_start;
uint32_t opcode;
int mem_idx;
uint16_t mem_idx;
uint16_t plv;
TCGv zero;
/* Space for 3 operands plus 1 extra for address computation. */
TCGv temp[4];