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RISC-V: Adding XTheadBa ISA extension 

This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Christoph Müllner 2023-01-31 21:20:02 +01:00 committed by Alistair Francis
parent 134c3ffa34
commit c9410a689f
5 changed files with 66 additions and 1 deletions
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2
target/riscv/cpu.c
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@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),

1
target/riscv/cpu.h
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@ -473,6 +473,7 @@ struct RISCVCPUConfig {
uint64_t mimpid;
/* Vendor-specific custom extensions */
bool ext_xtheadba;
bool ext_xtheadcmo;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;

39
target/riscv/insn_trans/trans_xthead.c.inc
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@ -16,6 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#define REQUIRE_XTHEADBA(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadba) { \
return false; \
} \
} while (0)
#define REQUIRE_XTHEADCMO(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadcmo) { \
return false; \
@ -28,6 +34,39 @@
} \
} while (0)
/* XTheadBa */
/*
* th.addsl is similar to sh[123]add (from Zba), but not an
* alternative encoding: while sh[123] applies the shift to rs1,
* th.addsl shifts rs2.
*/
#define GEN_TH_ADDSL(SHAMT) \
static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
{ \
TCGv t = tcg_temp_new(); \
tcg_gen_shli_tl(t, arg2, SHAMT); \
tcg_gen_add_tl(ret, t, arg1); \
tcg_temp_free(t); \
}
GEN_TH_ADDSL(1)
GEN_TH_ADDSL(2)
GEN_TH_ADDSL(3)
#define GEN_TRANS_TH_ADDSL(SHAMT) \
static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
arg_th_addsl##SHAMT * a) \
{ \
REQUIRE_XTHEADBA(ctx); \
return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
}
GEN_TRANS_TH_ADDSL(1)
GEN_TRANS_TH_ADDSL(2)
GEN_TRANS_TH_ADDSL(3)
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)

3
target/riscv/translate.c
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@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
{
return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \

22
target/riscv/xthead.decode
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@ -2,6 +2,7 @@
# Translation routines for the instructions of the XThead* ISA extensions
#
# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
@ -9,12 +10,33 @@
# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
# Fields:
%rd 7:5
%rs1 15:5
%rs2 20:5
# Argument sets
&r rd rs1 rs2 !extern
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
# XTheadBa
# Instead of defining a new encoding, we simply use the decoder to
# extract the imm[0:1] field and dispatch to separate translation
# functions (mirroring the `sh[123]add` instructions from Zba and
# the regular RVI `add` instruction.
#
# The only difference between sh[123]add and addsl is that the shift
# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
#
# Note that shift-by-0 is a valid operation according to the manual.
# This will be equivalent to a regular add.
add 0000000 ..... ..... 001 ..... 0001011 @r
th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
# XTheadCmo
th_dcache_call 0000000 00001 00000 000 00000 0001011