MIPS queue for October 2018 - part 2 - v2
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABAgAGBQJb0HIuAAoJENSXKoln91plGcUH/3Lje5KF8kkShQ5dIrH9e8Xz bvK6lXOLNnndEyrWqJNLaJs7eJKEV2N+E2sBmdIjKnWXVHW6gOW3QBMuVGPTT4rg C6cntrh2HpnxibgJqrR+3RmjQHAI1Ktixhker9LWimF3ZZhcy4H6mFHwW9z7eBK4 +n/pbnk8fq4FlGHJ2teHhctVIma6slmd8lkMa9vdwVQwpAyzpP82XjrsoTeeYhmG uuTvX3TFnXKGa9mYGxybpwKd4i+397l9fTQ4egx1KlZMR8OHuQItCBDOFdiQpHOg yljCeG3jHEhNzVf+xW7JU692Lz097otWDbzWDJibYGJkdkhKfyHJ9PvCYaPiK6M= =Sg8J -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2' into staging MIPS queue for October 2018 - part 2 - v2 # gpg: Signature made Wed 24 Oct 2018 14:22:54 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-oct-2018-part-2-v2: (33 commits) target/mips: Fix decoding of ALIGN and DALIGN instructions target/mips: Fix the title of translate.c linux-user/mips: Recognize the R5900 CPU model target/mips: Define the R5900 CPU tests/tcg/mips: Add tests for R5900 DIVU1 tests/tcg/mips: Add tests for R5900 DIV1 tests/tcg/mips: Add tests for R5900 MTLO1 and MTHI1 tests/tcg/mips: Add tests for R5900 MFLO1 and MFHI1 tests/tcg/mips: Add tests for R5900 three-operand MULTU1 tests/tcg/mips: Add tests for R5900 three-operand MULT1 tests/tcg/mips: Add tests for R5900 three-operand MULTU tests/tcg/mips: Add tests for R5900 three-operand MULT target/mips: Make R5900 DMULT[U], DDIV[U], LL[D] and SC[D] user only target/mips: Support R5900 MOVN, MOVZ and PREF instructions from MIPS IV target/mips: Support R5900 DIV1 and DIVU1 instructions target/mips: Support R5900 MFLO1, MTLO1, MFHI1 and MTHI1 instructions target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions target/mips: Support R5900 three-operand MULT and MULTU instructions target/mips: Add a placeholder for R5900 MMI3 instruction subclass target/mips: Add a placeholder for R5900 MMI2 instruction subclass ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
c96292036a
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@ -12,6 +12,9 @@ static inline const char *cpu_get_model(uint32_t eflags)
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if ((eflags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) {
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return "mips32r6-generic";
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}
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if ((eflags & EF_MIPS_MACH) == EF_MIPS_MACH_5900) {
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return "R5900";
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}
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return "24Kf";
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}
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#endif
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@ -64,9 +64,11 @@
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#define INSN_LOONGSON2E 0x0001000000000000ULL
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#define INSN_LOONGSON2F 0x0002000000000000ULL
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#define INSN_VR54XX 0x0004000000000000ULL
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#define INSN_R5900 0x0008000000000000ULL
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/*
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* bits 56-63: vendor-specific ASEs
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*/
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#define ASE_MMI 0x0100000000000000ULL
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/* MIPS CPU defines. */
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#define CPU_MIPS1 (ISA_MIPS1)
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@ -74,6 +76,7 @@
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#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
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#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
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#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
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#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
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#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
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#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
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File diff suppressed because it is too large
Load Diff
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@ -410,6 +410,65 @@ const mips_def_t mips_defs[] =
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.insn_flags = CPU_MIPS32R5 | ASE_MSA,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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/*
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* The Toshiba TX System RISC TX79 Core Architecture manual
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*
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* https://wiki.qemu.org/File:C790.pdf
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*
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* describes the C790 processor that is a follow-up to the R5900.
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* There are a few notable differences in that the R5900 FPU
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*
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* - is not IEEE 754-1985 compliant,
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* - does not implement double format, and
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* - its machine code is nonstandard.
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*/
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.name = "R5900",
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.CP0_PRid = 0x00002E00,
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/* No L2 cache, icache size 32k, dcache size 32k, uncached coherency. */
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.CP0_Config0 = (0x3 << 9) | (0x3 << 6) | (0x2 << CP0C0_K0),
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.CP0_Status_rw_bitmask = 0xF4C79C1F,
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#ifdef CONFIG_USER_ONLY
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/*
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* R5900 hardware traps to the Linux kernel for IEEE 754-1985 and LL/SC
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* emulation. For user only, QEMU is the kernel, so we emulate the traps
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* by simply emulating the instructions directly.
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*
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* Note: Config1 is only used internally, the R5900 has only Config0.
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*/
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.CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
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.CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
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.CP0_LLAddr_shift = 4,
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.CP1_fcr0 = (0x38 << FCR0_PRID) | (0x0 << FCR0_REV),
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.CP1_fcr31 = 0,
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.CP1_fcr31_rw_bitmask = 0x0183FFFF,
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#else
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/*
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* The R5900 COP1 FPU implements single-precision floating-point
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* operations but is not entirely IEEE 754-1985 compatible. In
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* particular,
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*
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* - NaN (not a number) and +/- infinities are not supported;
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* - exception mechanisms are not fully supported;
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* - denormalized numbers are not supported;
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* - rounding towards nearest and +/- infinities are not supported;
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* - computed results usually differs in the least significant bit;
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* - saturations can differ more than the least significant bit.
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*
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* Since only rounding towards zero is supported, the two least
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* significant bits of FCR31 are hardwired to 01.
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*
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* FPU emulation is disabled here until it is implemented.
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*
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* Note: Config1 is only used internally, the R5900 has only Config0.
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*/
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.CP0_Config1 = (47 << CP0C1_MMU),
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#endif /* !CONFIG_USER_ONLY */
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.SEGBITS = 32,
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.PABITS = 32,
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.insn_flags = CPU_R5900 | ASE_MMI,
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.mmu_type = MMU_TYPE_R4000,
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},
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{
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/* A generic CPU supporting MIPS32 Release 6 ISA.
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FIXME: Support IEEE 754-2008 FP.
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@ -0,0 +1,30 @@
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-include ../../config-host.mak
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CROSS=mipsr5900el-unknown-linux-gnu-
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SIM=qemu-mipsel
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SIM_FLAGS=-cpu R5900
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CC = $(CROSS)gcc
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CFLAGS = -Wall -mabi=32 -march=r5900 -static
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TESTCASES = div1.tst
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TESTCASES += divu1.tst
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TESTCASES += mflohi1.tst
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TESTCASES += mtlohi1.tst
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TESTCASES += mult.tst
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TESTCASES += multu.tst
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all: $(TESTCASES)
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%.tst: %.c
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$(CC) $(CFLAGS) $< -o $@
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check: $(TESTCASES)
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@for case in $(TESTCASES); do \
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echo $(SIM) $(SIM_FLAGS) ./$$case;\
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$(SIM) $(SIM_FLAGS) ./$$case; \
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done
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clean:
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$(RM) -rf $(TESTCASES)
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@ -0,0 +1,73 @@
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/*
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* Test R5900-specific DIV1.
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*/
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#include <stdio.h>
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#include <inttypes.h>
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#include <assert.h>
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struct quotient_remainder { int32_t quotient, remainder; };
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static struct quotient_remainder div1(int32_t rs, int32_t rt)
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{
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int32_t lo, hi;
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__asm__ __volatile__ (
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" div1 $0, %2, %3\n"
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" mflo1 %0\n"
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" mfhi1 %1\n"
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: "=r" (lo), "=r" (hi)
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: "r" (rs), "r" (rt));
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assert(rs / rt == lo);
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assert(rs % rt == hi);
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return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
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}
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static void verify_div1(int32_t rs, int32_t rt,
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int32_t expected_quotient,
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int32_t expected_remainder)
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{
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struct quotient_remainder qr = div1(rs, rt);
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assert(qr.quotient == expected_quotient);
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assert(qr.remainder == expected_remainder);
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}
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static void verify_div1_negations(int32_t rs, int32_t rt,
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int32_t expected_quotient,
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int32_t expected_remainder)
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{
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verify_div1(rs, rt, expected_quotient, expected_remainder);
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verify_div1(rs, -rt, -expected_quotient, expected_remainder);
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verify_div1(-rs, rt, -expected_quotient, -expected_remainder);
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verify_div1(-rs, -rt, expected_quotient, -expected_remainder);
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}
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int main()
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{
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verify_div1_negations(0, 1, 0, 0);
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verify_div1_negations(1, 1, 1, 0);
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verify_div1_negations(1, 2, 0, 1);
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verify_div1_negations(17, 19, 0, 17);
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verify_div1_negations(19, 17, 1, 2);
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verify_div1_negations(77773, 101, 770, 3);
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verify_div1(-0x80000000, 1, -0x80000000, 0);
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/*
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* Supplementary explanation from the Toshiba TX System RISC TX79 Core
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* Architecture manual, A-38 and B-7, https://wiki.qemu.org/File:C790.pdf
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*
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* Normally, when 0x80000000 (-2147483648) the signed minimum value is
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* divided by 0xFFFFFFFF (-1), the operation will result in an overflow.
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* However, in this instruction an overflow exception doesn't occur and
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* the result will be as follows:
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*
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* Quotient is 0x80000000 (-2147483648), and remainder is 0x00000000 (0).
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*/
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verify_div1(-0x80000000, -1, -0x80000000, 0);
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return 0;
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}
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@ -0,0 +1,48 @@
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/*
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* Test R5900-specific DIVU1.
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*/
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#include <stdio.h>
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#include <inttypes.h>
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#include <assert.h>
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struct quotient_remainder { uint32_t quotient, remainder; };
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static struct quotient_remainder divu1(uint32_t rs, uint32_t rt)
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{
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uint32_t lo, hi;
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__asm__ __volatile__ (
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" divu1 $0, %2, %3\n"
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" mflo1 %0\n"
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" mfhi1 %1\n"
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: "=r" (lo), "=r" (hi)
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: "r" (rs), "r" (rt));
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assert(rs / rt == lo);
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assert(rs % rt == hi);
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return (struct quotient_remainder) { .quotient = lo, .remainder = hi };
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}
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static void verify_divu1(uint32_t rs, uint32_t rt,
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uint32_t expected_quotient,
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uint32_t expected_remainder)
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{
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struct quotient_remainder qr = divu1(rs, rt);
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assert(qr.quotient == expected_quotient);
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assert(qr.remainder == expected_remainder);
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}
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int main()
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{
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verify_divu1(0, 1, 0, 0);
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verify_divu1(1, 1, 1, 0);
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verify_divu1(1, 2, 0, 1);
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verify_divu1(17, 19, 0, 17);
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verify_divu1(19, 17, 1, 2);
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verify_divu1(77773, 101, 770, 3);
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return 0;
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}
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@ -0,0 +1,35 @@
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/*
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* Test R5900-specific MFLO1 and MFHI1.
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*/
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#include <stdio.h>
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#include <inttypes.h>
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#include <assert.h>
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int main()
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{
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int32_t rs = 12207031, rt = 305175781;
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int32_t rs1 = 32452867, rt1 = 49979687;
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int64_t lo, hi, lo1, hi1;
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int64_t r, r1;
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/* Test both LO/HI and LO1/HI1 to verify separation. */
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__asm__ __volatile__ (
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" mult $0, %4, %5\n"
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" mult1 $0, %6, %7\n"
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" mflo %0\n"
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" mfhi %1\n"
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" mflo1 %2\n"
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" mfhi1 %3\n"
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: "=r" (lo), "=r" (hi),
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"=r" (lo1), "=r" (hi1)
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: "r" (rs), "r" (rt),
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"r" (rs1), "r" (rt1));
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r = ((int64_t)hi << 32) | (uint32_t)lo;
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r1 = ((int64_t)hi1 << 32) | (uint32_t)lo1;
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assert(r == 3725290219116211);
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assert(r1 == 1621984134912629);
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return 0;
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}
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@ -0,0 +1,40 @@
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/*
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* Test R5900-specific MTLO1 and MTHI1.
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*/
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#include <stdio.h>
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#include <inttypes.h>
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#include <assert.h>
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int main()
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{
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int32_t tlo = 12207031, thi = 305175781;
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int32_t tlo1 = 32452867, thi1 = 49979687;
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int32_t flo, fhi, flo1, fhi1;
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/* Test both LO/HI and LO1/HI1 to verify separation. */
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__asm__ __volatile__ (
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" mtlo %4\n"
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" mthi %5\n"
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" mtlo1 %6\n"
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" mthi1 %7\n"
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" move %0, $0\n"
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" move %1, $0\n"
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" move %2, $0\n"
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" move %3, $0\n"
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" mflo %0\n"
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" mfhi %1\n"
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" mflo1 %2\n"
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" mfhi1 %3\n"
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: "=r" (flo), "=r" (fhi),
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"=r" (flo1), "=r" (fhi1)
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: "r" (tlo), "r" (thi),
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"r" (tlo1), "r" (thi1));
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assert(flo == 12207031);
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assert(fhi == 305175781);
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assert(flo1 == 32452867);
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assert(fhi1 == 49979687);
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return 0;
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}
|
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|
|
@ -0,0 +1,76 @@
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/*
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* Test R5900-specific three-operand MULT and MULT1.
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*/
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|
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#include <stdio.h>
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#include <inttypes.h>
|
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#include <assert.h>
|
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|
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static int64_t mult(int32_t rs, int32_t rt)
|
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{
|
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int32_t rd, lo, hi;
|
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int64_t r;
|
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|
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__asm__ __volatile__ (
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" mult %0, %3, %4\n"
|
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" mflo %1\n"
|
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" mfhi %2\n"
|
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: "=r" (rd), "=r" (lo), "=r" (hi)
|
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: "r" (rs), "r" (rt));
|
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r = ((int64_t)hi << 32) | (uint32_t)lo;
|
||||
|
||||
assert((int64_t)rs * rt == r);
|
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assert(rd == lo);
|
||||
|
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return r;
|
||||
}
|
||||
|
||||
static int64_t mult1(int32_t rs, int32_t rt)
|
||||
{
|
||||
int32_t rd, lo, hi;
|
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int64_t r;
|
||||
|
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__asm__ __volatile__ (
|
||||
" mult1 %0, %3, %4\n"
|
||||
" mflo1 %1\n"
|
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" mfhi1 %2\n"
|
||||
: "=r" (rd), "=r" (lo), "=r" (hi)
|
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: "r" (rs), "r" (rt));
|
||||
r = ((int64_t)hi << 32) | (uint32_t)lo;
|
||||
|
||||
assert((int64_t)rs * rt == r);
|
||||
assert(rd == lo);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int64_t mult_variants(int32_t rs, int32_t rt)
|
||||
{
|
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int64_t rd = mult(rs, rt);
|
||||
int64_t rd1 = mult1(rs, rt);
|
||||
|
||||
assert(rd == rd1);
|
||||
|
||||
return rd;
|
||||
}
|
||||
|
||||
static void verify_mult_negations(int32_t rs, int32_t rt, int64_t expected)
|
||||
{
|
||||
assert(mult_variants(rs, rt) == expected);
|
||||
assert(mult_variants(-rs, rt) == -expected);
|
||||
assert(mult_variants(rs, -rt) == -expected);
|
||||
assert(mult_variants(-rs, -rt) == expected);
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
verify_mult_negations(17, 19, 323);
|
||||
verify_mult_negations(77773, 99991, 7776600043);
|
||||
verify_mult_negations(12207031, 305175781, 3725290219116211);
|
||||
|
||||
assert(mult_variants(-0x80000000, 0x7FFFFFFF) == -0x3FFFFFFF80000000);
|
||||
assert(mult_variants(-0x80000000, -0x7FFFFFFF) == 0x3FFFFFFF80000000);
|
||||
assert(mult_variants(-0x80000000, -0x80000000) == 0x4000000000000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
/*
|
||||
* Test R5900-specific three-operand MULTU and MULTU1.
|
||||
*/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <inttypes.h>
|
||||
#include <assert.h>
|
||||
|
||||
static uint64_t multu(uint32_t rs, uint32_t rt)
|
||||
{
|
||||
uint32_t rd, lo, hi;
|
||||
uint64_t r;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" multu %0, %3, %4\n"
|
||||
" mflo %1\n"
|
||||
" mfhi %2\n"
|
||||
: "=r" (rd), "=r" (lo), "=r" (hi)
|
||||
: "r" (rs), "r" (rt));
|
||||
r = ((uint64_t)hi << 32) | (uint32_t)lo;
|
||||
|
||||
assert((uint64_t)rs * rt == r);
|
||||
assert(rd == lo);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static uint64_t multu1(uint32_t rs, uint32_t rt)
|
||||
{
|
||||
uint32_t rd, lo, hi;
|
||||
uint64_t r;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
" multu1 %0, %3, %4\n"
|
||||
" mflo1 %1\n"
|
||||
" mfhi1 %2\n"
|
||||
: "=r" (rd), "=r" (lo), "=r" (hi)
|
||||
: "r" (rs), "r" (rt));
|
||||
r = ((uint64_t)hi << 32) | (uint32_t)lo;
|
||||
|
||||
assert((uint64_t)rs * rt == r);
|
||||
assert(rd == lo);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static uint64_t multu_variants(uint32_t rs, uint32_t rt)
|
||||
{
|
||||
uint64_t rd = multu(rs, rt);
|
||||
uint64_t rd1 = multu1(rs, rt);
|
||||
|
||||
assert(rd == rd1);
|
||||
|
||||
return rd;
|
||||
}
|
||||
|
||||
int main()
|
||||
{
|
||||
assert(multu_variants(17, 19) == 323);
|
||||
assert(multu_variants(77773, 99991) == 7776600043);
|
||||
assert(multu_variants(12207031, 305175781) == 3725290219116211);
|
||||
|
||||
assert(multu_variants(0x80000000U, 0x7FFFFFFF) == 0x3FFFFFFF80000000);
|
||||
assert(multu_variants(0x80000000U, 0x80000000U) == 0x4000000000000000);
|
||||
assert(multu_variants(0xFFFFFFFFU, 0xFFFFFFFFU) == 0xFFFFFFFE00000001U);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue