ARM MPCore tweaks
Allow the user to specify the number of cores present on the RealView EB + ARM11MPCore board. Also split into its own config rather than guessing from the CPU name. Signed-off-by: Paul Brook <paul@codesourcery.com>
This commit is contained in:
Paul Brook
parent
26e92f6552
commit
c988bfadc9
28
hw/arm_gic.c
28
hw/arm_gic.c
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@ -48,6 +48,11 @@ typedef struct gic_irq_state
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} gic_irq_state;
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#define ALL_CPU_MASK ((1 << NCPU) - 1)
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#if NCPU > 1
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#define NUM_CPU(s) ((s)->num_cpu)
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#else
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#define NUM_CPU(s) 1
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#endif
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#define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
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#define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
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@ -95,6 +100,10 @@ typedef struct gic_state
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int running_priority[NCPU];
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int current_pending[NCPU];
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#if NCPU > 1
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int num_cpu;
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#endif
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int iomemtype;
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} gic_state;
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@ -109,7 +118,7 @@ static void gic_update(gic_state *s)
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int cpu;
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int cm;
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for (cpu = 0; cpu < NCPU; cpu++) {
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for (cpu = 0; cpu < NUM_CPU(s); cpu++) {
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cm = 1 << cpu;
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s->current_pending[cpu] = 1023;
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if (!s->enabled || !s->cpu_enabled[cpu]) {
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@ -255,7 +264,7 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
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if (offset == 0)
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return s->enabled;
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if (offset == 4)
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return ((GIC_NIRQ / 32) - 1) | ((NCPU - 1) << 5);
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return ((GIC_NIRQ / 32) - 1) | ((NUM_CPU(s) - 1) << 5);
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if (offset < 0x08)
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return 0;
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#endif
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@ -620,7 +629,7 @@ static void gic_reset(gic_state *s)
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{
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int i;
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memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
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for (i = 0 ; i < NCPU; i++) {
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for (i = 0 ; i < NUM_CPU(s); i++) {
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s->priority_mask[i] = 0xf0;
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s->current_pending[i] = 1023;
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s->running_irq[i] = 1023;
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@ -651,7 +660,7 @@ static void gic_save(QEMUFile *f, void *opaque)
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int j;
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qemu_put_be32(f, s->enabled);
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for (i = 0; i < NCPU; i++) {
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for (i = 0; i < NUM_CPU(s); i++) {
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qemu_put_be32(f, s->cpu_enabled[i]);
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#ifndef NVIC
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qemu_put_be32(f, s->irq_target[i]);
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@ -688,7 +697,7 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
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return -EINVAL;
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s->enabled = qemu_get_be32(f);
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for (i = 0; i < NCPU; i++) {
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for (i = 0; i < NUM_CPU(s); i++) {
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s->cpu_enabled[i] = qemu_get_be32(f);
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#ifndef NVIC
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s->irq_target[i] = qemu_get_be32(f);
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@ -717,12 +726,19 @@ static int gic_load(QEMUFile *f, void *opaque, int version_id)
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return 0;
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}
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#if NCPU > 1
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static void gic_init(gic_state *s, int num_cpu)
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#else
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static void gic_init(gic_state *s)
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#endif
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{
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int i;
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#if NCPU > 1
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s->num_cpu = num_cpu;
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#endif
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qdev_init_gpio_in(&s->busdev.qdev, gic_set_irq, GIC_NIRQ - 32);
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for (i = 0; i < NCPU; i++) {
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for (i = 0; i < NUM_CPU(s); i++) {
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sysbus_init_irq(&s->busdev, &s->parent_irq[i]);
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}
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s->iomemtype = cpu_register_io_memory(gic_dist_readfn,
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64
hw/mpcore.c
64
hw/mpcore.c
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@ -44,6 +44,7 @@ typedef struct mpcore_priv_state {
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uint32_t scu_control;
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int iomemtype;
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mpcore_timer_state timer[8];
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uint32_t num_cpu;
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} mpcore_priv_state;
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/* Per-CPU Timers. */
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@ -166,7 +167,8 @@ static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
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case 0x00: /* Control. */
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return s->scu_control;
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case 0x04: /* Configuration. */
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return 0xf3;
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id = ((1 << s->num_cpu) - 1) << 4;
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return id | (s->num_cpu - 1);
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case 0x08: /* CPU status. */
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return 0;
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case 0x0c: /* Invalidate all. */
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@ -180,6 +182,9 @@ static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x200) >> 8;
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if (id >= s->num_cpu) {
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return 0;
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}
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}
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return gic_cpu_read(&s->gic, id, offset & 0xff);
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} else if (offset < 0xb00) {
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@ -188,6 +193,9 @@ static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x700) >> 8;
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if (id >= s->num_cpu) {
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return 0;
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}
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}
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id <<= 1;
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if (offset & 0x20)
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@ -224,7 +232,9 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
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} else {
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id = (offset - 0x200) >> 8;
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}
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gic_cpu_write(&s->gic, id, offset & 0xff, value);
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if (id < s->num_cpu) {
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gic_cpu_write(&s->gic, id, offset & 0xff, value);
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}
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} else if (offset < 0xb00) {
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/* Timers. */
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if (offset < 0x700) {
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@ -232,10 +242,12 @@ static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
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} else {
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id = (offset - 0x700) >> 8;
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}
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id <<= 1;
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if (offset & 0x20)
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id++;
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mpcore_timer_write(&s->timer[id], offset & 0xf, value);
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if (id < s->num_cpu) {
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id <<= 1;
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if (offset & 0x20)
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id++;
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mpcore_timer_write(&s->timer[id], offset & 0xf, value);
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}
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return;
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}
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return;
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@ -267,11 +279,11 @@ static int mpcore_priv_init(SysBusDevice *dev)
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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int i;
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gic_init(&s->gic);
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gic_init(&s->gic, s->num_cpu);
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s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
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mpcore_priv_writefn, s);
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sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
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for (i = 0; i < 8; i++) {
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for (i = 0; i < s->num_cpu * 2; i++) {
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mpcore_timer_init(s, &s->timer[i], i);
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}
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return 0;
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@ -284,6 +296,7 @@ typedef struct {
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SysBusDevice busdev;
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qemu_irq cpuic[32];
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qemu_irq rvic[4][64];
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uint32_t num_cpu;
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} mpcore_rirq_state;
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/* Map baseboard IRQs onto CPU IRQ lines. */
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@ -315,11 +328,16 @@ static int realview_mpcore_init(SysBusDevice *dev)
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mpcore_rirq_state *s = FROM_SYSBUS(mpcore_rirq_state, dev);
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DeviceState *gic;
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DeviceState *priv;
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SysBusDevice *bus_priv;
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int n;
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int i;
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priv = sysbus_create_simple("arm11mpcore_priv", MPCORE_PRIV_BASE, NULL);
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sysbus_pass_irq(dev, sysbus_from_qdev(priv));
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priv = qdev_create(NULL, "arm11mpcore_priv");
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qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
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qdev_init_nofail(priv);
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bus_priv = sysbus_from_qdev(priv);
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sysbus_mmio_map(bus_priv, 0, MPCORE_PRIV_BASE);
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sysbus_pass_irq(dev, bus_priv);
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for (i = 0; i < 32; i++) {
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s->cpuic[i] = qdev_get_gpio_in(priv, i);
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}
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@ -335,12 +353,30 @@ static int realview_mpcore_init(SysBusDevice *dev)
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return 0;
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}
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static SysBusDeviceInfo mpcore_rirq_info = {
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.init = realview_mpcore_init,
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.qdev.name = "realview_mpcore",
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.qdev.size = sizeof(mpcore_rirq_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static SysBusDeviceInfo mpcore_priv_info = {
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.init = mpcore_priv_init,
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.qdev.name = "arm11mpcore_priv",
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.qdev.size = sizeof(mpcore_priv_state),
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.qdev.props = (Property[]) {
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DEFINE_PROP_UINT32("num-cpu", mpcore_priv_state, num_cpu, 1),
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DEFINE_PROP_END_OF_LIST(),
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}
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};
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static void mpcore_register_devices(void)
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{
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sysbus_register_dev("realview_mpcore", sizeof(mpcore_rirq_state),
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realview_mpcore_init);
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sysbus_register_dev("arm11mpcore_priv", sizeof(mpcore_priv_state),
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mpcore_priv_init);
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sysbus_register_withprop(&mpcore_rirq_info);
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sysbus_register_withprop(&mpcore_priv_info);
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}
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device_init(mpcore_register_devices)
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@ -35,14 +35,21 @@ static void secondary_cpu_reset(void *opaque)
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env->regs[15] = 0x80000000;
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}
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enum realview_board_type {
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BOARD_EB,
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BOARD_EB_MPCORE
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};
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static void realview_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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const char *initrd_filename, const char *cpu_model,
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enum realview_board_type board_type)
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{
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CPUState *env;
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CPUState *env = NULL;
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ram_addr_t ram_offset;
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DeviceState *dev;
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SysBusDevice *busdev;
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qemu_irq *irqp;
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qemu_irq pic[64];
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PCIBus *pci_bus;
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@ -50,19 +57,10 @@ static void realview_init(ram_addr_t ram_size,
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int n;
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int done_smc = 0;
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qemu_irq cpu_irq[4];
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int ncpu;
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int is_mpcore = (board_type == BOARD_EB_MPCORE);
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uint32_t proc_id = 0;
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if (!cpu_model)
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cpu_model = "arm926";
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/* FIXME: obey smp_cpus. */
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if (strcmp(cpu_model, "arm11mpcore") == 0) {
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ncpu = 4;
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} else {
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ncpu = 1;
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}
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for (n = 0; n < ncpu; n++) {
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for (n = 0; n < smp_cpus; n++) {
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find CPU definition\n");
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@ -91,15 +89,16 @@ static void realview_init(ram_addr_t ram_size,
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arm_sysctl_init(0x10000000, 0xc1400400, proc_id);
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if (ncpu == 1) {
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/* ??? The documentation says GIC1 is nFIQ and either GIC2 or GIC3
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is nIRQ (there are inconsistencies). However Linux 2.6.17 expects
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GIC1 to be nIRQ and ignores all the others, so do that for now. */
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dev = sysbus_create_simple("realview_gic", 0x10040000, cpu_irq[0]);
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if (is_mpcore) {
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dev = qdev_create(NULL, "realview_mpcore");
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qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
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qdev_init_nofail(dev);
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busdev = sysbus_from_qdev(dev);
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for (n = 0; n < smp_cpus; n++) {
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sysbus_connect_irq(busdev, n, cpu_irq[n]);
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}
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} else {
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dev = sysbus_create_varargs("realview_mpcore", -1,
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cpu_irq[0], cpu_irq[1], cpu_irq[2],
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cpu_irq[3], NULL);
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dev = sysbus_create_simple("realview_gic", 0x10040000, cpu_irq[0]);
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}
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for (n = 0; n < 64; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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@ -210,20 +209,53 @@ static void realview_init(ram_addr_t ram_size,
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realview_binfo.kernel_filename = kernel_filename;
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realview_binfo.kernel_cmdline = kernel_cmdline;
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realview_binfo.initrd_filename = initrd_filename;
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realview_binfo.nb_cpus = ncpu;
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realview_binfo.nb_cpus = smp_cpus;
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arm_load_kernel(first_cpu, &realview_binfo);
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}
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static QEMUMachine realview_machine = {
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.name = "realview",
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static void realview_eb_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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if (!cpu_model) {
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cpu_model = "arm926";
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}
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realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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initrd_filename, cpu_model, BOARD_EB);
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}
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static void realview_eb_mpcore_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename, const char *cpu_model)
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{
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if (!cpu_model) {
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cpu_model = "arm11mpcore";
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}
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realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
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initrd_filename, cpu_model, BOARD_EB_MPCORE);
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}
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static QEMUMachine realview_eb_machine = {
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.name = "realview-eb",
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.desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
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.init = realview_init,
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.init = realview_eb_init,
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.use_scsi = 1,
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};
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static QEMUMachine realview_eb_mpcore_machine = {
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.name = "realview-eb-mpcore",
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.desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
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.init = realview_eb_mpcore_init,
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.use_scsi = 1,
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.max_cpus = 4,
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};
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static void realview_machine_init(void)
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{
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qemu_register_machine(&realview_machine);
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qemu_register_machine(&realview_eb_machine);
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qemu_register_machine(&realview_eb_mpcore_machine);
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}
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machine_init(realview_machine_init);
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@ -1663,7 +1663,7 @@ The ARM RealView Emulation baseboard is emulated with the following devices:
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@itemize @minus
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@item
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ARM926E, ARM1136, ARM11MPCORE(x4) or Cortex-A8 CPU
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ARM926E, ARM1136, ARM11MPCORE or Cortex-A8 CPU
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@item
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ARM AMBA Generic/Distributed Interrupt Controller
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@item
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