target-sparc: implement NPT timer bit
If the NPT bit is set in the timer register, all non-supervisor read accesses to the register should fail with a privilege exception. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-By: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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@ -51,10 +51,16 @@ void helper_tick_set_count(void *opaque, uint64_t count)
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#endif
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}
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uint64_t helper_tick_get_count(void *opaque)
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uint64_t helper_tick_get_count(CPUSPARCState *env, void *opaque, int mem_idx)
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{
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#if !defined(CONFIG_USER_ONLY)
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return cpu_tick_get_count(opaque);
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CPUTimer *timer = opaque;
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if (timer->npt && mem_idx < MMU_KERNEL_IDX) {
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helper_raise_exception(env, TT_PRIV_INSN);
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}
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return cpu_tick_get_count(timer);
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#else
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return 0;
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#endif
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@ -25,7 +25,7 @@ DEF_HELPER_2(set_softint, void, env, i64)
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DEF_HELPER_2(clear_softint, void, env, i64)
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DEF_HELPER_2(write_softint, void, env, i64)
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DEF_HELPER_2(tick_set_count, void, ptr, i64)
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DEF_HELPER_1(tick_get_count, i64, ptr)
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DEF_HELPER_3(tick_get_count, i64, env, ptr, int)
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DEF_HELPER_2(tick_set_limit, void, ptr, i64)
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#endif
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#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
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@ -2708,12 +2708,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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case 0x4: /* V9 rdtick */
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{
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TCGv_ptr r_tickptr;
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TCGv_i32 r_const;
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r_tickptr = tcg_temp_new_ptr();
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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gen_helper_tick_get_count(cpu_dst, r_tickptr);
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gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
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r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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}
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break;
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@ -2750,12 +2754,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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case 0x18: /* System tick */
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{
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TCGv_ptr r_tickptr;
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TCGv_i32 r_const;
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r_tickptr = tcg_temp_new_ptr();
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, stick));
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gen_helper_tick_get_count(cpu_dst, r_tickptr);
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gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
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r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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gen_store_gpr(dc, rd, cpu_dst);
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}
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break;
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@ -2863,12 +2871,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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case 4: // tick
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{
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TCGv_ptr r_tickptr;
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TCGv_i32 r_const;
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r_tickptr = tcg_temp_new_ptr();
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r_const = tcg_const_i32(dc->mem_idx);
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tcg_gen_ld_ptr(r_tickptr, cpu_env,
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offsetof(CPUSPARCState, tick));
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gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
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gen_helper_tick_get_count(cpu_tmp0, cpu_env,
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r_tickptr, r_const);
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tcg_temp_free_ptr(r_tickptr);
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tcg_temp_free_i32(r_const);
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}
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break;
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case 5: // tba
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