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target-sparc: implement NPT timer bit 

If the NPT bit is set in the timer register, all non-supervisor read accesses
to the register should fail with a privilege exception.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-By: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This commit is contained in:
Mark Cave-Ayland 2015-11-08 17:11:59 +00:00
parent bf43330aa4
commit c9a464420d
3 changed files with 24 additions and 6 deletions
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10
target-sparc/helper.c
View File

@ -51,10 +51,16 @@ void helper_tick_set_count(void *opaque, uint64_t count)
#endif
}
uint64_t helper_tick_get_count(void *opaque)
uint64_t helper_tick_get_count(CPUSPARCState *env, void *opaque, int mem_idx)
{
#if !defined(CONFIG_USER_ONLY)
return cpu_tick_get_count(opaque);
CPUTimer *timer = opaque;
if (timer->npt && mem_idx < MMU_KERNEL_IDX) {
helper_raise_exception(env, TT_PRIV_INSN);
}
return cpu_tick_get_count(timer);
#else
return 0;
#endif

2
target-sparc/helper.h
View File

@ -25,7 +25,7 @@ DEF_HELPER_2(set_softint, void, env, i64)
DEF_HELPER_2(clear_softint, void, env, i64)
DEF_HELPER_2(write_softint, void, env, i64)
DEF_HELPER_2(tick_set_count, void, ptr, i64)
DEF_HELPER_1(tick_get_count, i64, ptr)
DEF_HELPER_3(tick_get_count, i64, env, ptr, int)
DEF_HELPER_2(tick_set_limit, void, ptr, i64)
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)

18
target-sparc/translate.c
View File

@ -2708,12 +2708,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x4: /* V9 rdtick */
{
TCGv_ptr r_tickptr;
TCGv_i32 r_const;
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
gen_store_gpr(dc, rd, cpu_dst);
}
break;
@ -2750,12 +2754,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 0x18: /* System tick */
{
TCGv_ptr r_tickptr;
TCGv_i32 r_const;
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, stick));
gen_helper_tick_get_count(cpu_dst, r_tickptr);
gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr,
r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
gen_store_gpr(dc, rd, cpu_dst);
}
break;
@ -2863,12 +2871,16 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
case 4: // tick
{
TCGv_ptr r_tickptr;
TCGv_i32 r_const;
r_tickptr = tcg_temp_new_ptr();
r_const = tcg_const_i32(dc->mem_idx);
tcg_gen_ld_ptr(r_tickptr, cpu_env,
offsetof(CPUSPARCState, tick));
gen_helper_tick_get_count(cpu_tmp0, r_tickptr);
gen_helper_tick_get_count(cpu_tmp0, cpu_env,
r_tickptr, r_const);
tcg_temp_free_ptr(r_tickptr);
tcg_temp_free_i32(r_const);
}
break;
case 5: // tba