target/loongarch: Implement LASX fpu arith instructions
This patch includes:
- XVF{ADD/SUB/MUL/DIV}.{S/D};
- XVF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- XVF{MAX/MIN}.{S/D};
- XVF{MAXA/MINA}.{S/D};
- XVFLOGB.{S/D};
- XVFCLASS.{S/D};
- XVF{SQRT/RECIP/RSQRT}.{S/D}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-47-gaosong@loongson.cn>
This commit is contained in:
Song Gao
parent
abee168ea3
commit
c9caf1587a
@ -1708,6 +1708,11 @@ static void output_v_i_x(DisasContext *ctx, arg_v_i *a, const char *mnemonic)
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output(ctx, mnemonic, "x%d, 0x%x", a->vd, a->imm);
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}
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static void output_vvvv_x(DisasContext *ctx, arg_vvvv *a, const char *mnemonic)
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{
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output(ctx, mnemonic, "x%d, x%d, x%d, x%d", a->vd, a->vj, a->vk, a->va);
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}
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static void output_vvv_x(DisasContext *ctx, arg_vvv * a, const char *mnemonic)
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{
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output(ctx, mnemonic, "x%d, x%d, x%d", a->vd, a->vj, a->vk);
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@ -2240,6 +2245,47 @@ INSN_LASX(xvfrstp_h, vvv)
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INSN_LASX(xvfrstpi_b, vv_i)
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INSN_LASX(xvfrstpi_h, vv_i)
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INSN_LASX(xvfadd_s, vvv)
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INSN_LASX(xvfadd_d, vvv)
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INSN_LASX(xvfsub_s, vvv)
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INSN_LASX(xvfsub_d, vvv)
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INSN_LASX(xvfmul_s, vvv)
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INSN_LASX(xvfmul_d, vvv)
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INSN_LASX(xvfdiv_s, vvv)
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INSN_LASX(xvfdiv_d, vvv)
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INSN_LASX(xvfmadd_s, vvvv)
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INSN_LASX(xvfmadd_d, vvvv)
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INSN_LASX(xvfmsub_s, vvvv)
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INSN_LASX(xvfmsub_d, vvvv)
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INSN_LASX(xvfnmadd_s, vvvv)
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INSN_LASX(xvfnmadd_d, vvvv)
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INSN_LASX(xvfnmsub_s, vvvv)
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INSN_LASX(xvfnmsub_d, vvvv)
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INSN_LASX(xvfmax_s, vvv)
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INSN_LASX(xvfmax_d, vvv)
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INSN_LASX(xvfmin_s, vvv)
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INSN_LASX(xvfmin_d, vvv)
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INSN_LASX(xvfmaxa_s, vvv)
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INSN_LASX(xvfmaxa_d, vvv)
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INSN_LASX(xvfmina_s, vvv)
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INSN_LASX(xvfmina_d, vvv)
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INSN_LASX(xvflogb_s, vv)
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INSN_LASX(xvflogb_d, vv)
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INSN_LASX(xvfclass_s, vv)
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INSN_LASX(xvfclass_d, vv)
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INSN_LASX(xvfsqrt_s, vv)
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INSN_LASX(xvfsqrt_d, vv)
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INSN_LASX(xvfrecip_s, vv)
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INSN_LASX(xvfrecip_d, vv)
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INSN_LASX(xvfrsqrt_s, vv)
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INSN_LASX(xvfrsqrt_d, vv)
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INSN_LASX(xvreplgr2vr_b, vr)
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INSN_LASX(xvreplgr2vr_h, vr)
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INSN_LASX(xvreplgr2vr_w, vr)
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@ -33,6 +33,10 @@ static bool check_vec(DisasContext *ctx, uint32_t oprsz)
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static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
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gen_helper_gvec_4_ptr *fn)
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{
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if (!check_vec(ctx, oprsz)) {
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return true;
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}
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tcg_gen_gvec_4_ptr(vec_full_offset(a->vd),
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vec_full_offset(a->vj),
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vec_full_offset(a->vk),
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@ -45,13 +49,15 @@ static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
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static bool gen_vvvv_ptr(DisasContext *ctx, arg_vvvv *a,
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gen_helper_gvec_4_ptr *fn)
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{
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if (!check_vec(ctx, 16)) {
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return true;
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}
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return gen_vvvv_ptr_vl(ctx, a, 16, fn);
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}
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static bool gen_xxxx_ptr(DisasContext *ctx, arg_vvvv *a,
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gen_helper_gvec_4_ptr *fn)
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{
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return gen_vvvv_ptr_vl(ctx, a, 32, fn);
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}
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static bool gen_vvvv_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
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gen_helper_gvec_4 *fn)
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{
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@ -76,6 +82,9 @@ static bool gen_vvvv(DisasContext *ctx, arg_vvvv *a,
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static bool gen_vvv_ptr_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
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gen_helper_gvec_3_ptr *fn)
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{
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if (!check_vec(ctx, oprsz)) {
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return true;
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}
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tcg_gen_gvec_3_ptr(vec_full_offset(a->vd),
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vec_full_offset(a->vj),
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vec_full_offset(a->vk),
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@ -87,13 +96,15 @@ static bool gen_vvv_ptr_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
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static bool gen_vvv_ptr(DisasContext *ctx, arg_vvv *a,
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gen_helper_gvec_3_ptr *fn)
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{
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if (!check_vec(ctx, 16)) {
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return true;
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}
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return gen_vvv_ptr_vl(ctx, a, 16, fn);
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}
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static bool gen_xxx_ptr(DisasContext *ctx, arg_vvv *a,
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gen_helper_gvec_3_ptr *fn)
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{
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return gen_vvv_ptr_vl(ctx, a, 32, fn);
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}
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static bool gen_vvv_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
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gen_helper_gvec_3 *fn)
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{
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@ -121,6 +132,10 @@ static bool gen_xxx(DisasContext *ctx, arg_vvv *a, gen_helper_gvec_3 *fn)
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static bool gen_vv_ptr_vl(DisasContext *ctx, arg_vv *a, uint32_t oprsz,
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gen_helper_gvec_2_ptr *fn)
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{
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if (!check_vec(ctx, oprsz)) {
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return true;
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}
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tcg_gen_gvec_2_ptr(vec_full_offset(a->vd),
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vec_full_offset(a->vj),
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cpu_env,
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@ -131,13 +146,15 @@ static bool gen_vv_ptr_vl(DisasContext *ctx, arg_vv *a, uint32_t oprsz,
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static bool gen_vv_ptr(DisasContext *ctx, arg_vv *a,
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gen_helper_gvec_2_ptr *fn)
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{
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if (!check_vec(ctx, 16)) {
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return true;
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}
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return gen_vv_ptr_vl(ctx, a, 16, fn);
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}
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static bool gen_xx_ptr(DisasContext *ctx, arg_vv *a,
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gen_helper_gvec_2_ptr *fn)
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{
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return gen_vv_ptr_vl(ctx, a, 32, fn);
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}
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static bool gen_vv_vl(DisasContext *ctx, arg_vv *a, uint32_t oprsz,
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gen_helper_gvec_2 *fn)
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{
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@ -4313,6 +4330,14 @@ TRANS(vfmul_s, LSX, gen_vvv_ptr, gen_helper_vfmul_s)
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TRANS(vfmul_d, LSX, gen_vvv_ptr, gen_helper_vfmul_d)
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TRANS(vfdiv_s, LSX, gen_vvv_ptr, gen_helper_vfdiv_s)
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TRANS(vfdiv_d, LSX, gen_vvv_ptr, gen_helper_vfdiv_d)
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TRANS(xvfadd_s, LASX, gen_xxx_ptr, gen_helper_vfadd_s)
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TRANS(xvfadd_d, LASX, gen_xxx_ptr, gen_helper_vfadd_d)
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TRANS(xvfsub_s, LASX, gen_xxx_ptr, gen_helper_vfsub_s)
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TRANS(xvfsub_d, LASX, gen_xxx_ptr, gen_helper_vfsub_d)
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TRANS(xvfmul_s, LASX, gen_xxx_ptr, gen_helper_vfmul_s)
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TRANS(xvfmul_d, LASX, gen_xxx_ptr, gen_helper_vfmul_d)
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TRANS(xvfdiv_s, LASX, gen_xxx_ptr, gen_helper_vfdiv_s)
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TRANS(xvfdiv_d, LASX, gen_xxx_ptr, gen_helper_vfdiv_d)
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TRANS(vfmadd_s, LSX, gen_vvvv_ptr, gen_helper_vfmadd_s)
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TRANS(vfmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfmadd_d)
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@ -4322,22 +4347,42 @@ TRANS(vfnmadd_s, LSX, gen_vvvv_ptr, gen_helper_vfnmadd_s)
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TRANS(vfnmadd_d, LSX, gen_vvvv_ptr, gen_helper_vfnmadd_d)
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TRANS(vfnmsub_s, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_s)
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TRANS(vfnmsub_d, LSX, gen_vvvv_ptr, gen_helper_vfnmsub_d)
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TRANS(xvfmadd_s, LASX, gen_xxxx_ptr, gen_helper_vfmadd_s)
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TRANS(xvfmadd_d, LASX, gen_xxxx_ptr, gen_helper_vfmadd_d)
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TRANS(xvfmsub_s, LASX, gen_xxxx_ptr, gen_helper_vfmsub_s)
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TRANS(xvfmsub_d, LASX, gen_xxxx_ptr, gen_helper_vfmsub_d)
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TRANS(xvfnmadd_s, LASX, gen_xxxx_ptr, gen_helper_vfnmadd_s)
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TRANS(xvfnmadd_d, LASX, gen_xxxx_ptr, gen_helper_vfnmadd_d)
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TRANS(xvfnmsub_s, LASX, gen_xxxx_ptr, gen_helper_vfnmsub_s)
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TRANS(xvfnmsub_d, LASX, gen_xxxx_ptr, gen_helper_vfnmsub_d)
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TRANS(vfmax_s, LSX, gen_vvv_ptr, gen_helper_vfmax_s)
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TRANS(vfmax_d, LSX, gen_vvv_ptr, gen_helper_vfmax_d)
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TRANS(vfmin_s, LSX, gen_vvv_ptr, gen_helper_vfmin_s)
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TRANS(vfmin_d, LSX, gen_vvv_ptr, gen_helper_vfmin_d)
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TRANS(xvfmax_s, LASX, gen_xxx_ptr, gen_helper_vfmax_s)
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TRANS(xvfmax_d, LASX, gen_xxx_ptr, gen_helper_vfmax_d)
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TRANS(xvfmin_s, LASX, gen_xxx_ptr, gen_helper_vfmin_s)
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TRANS(xvfmin_d, LASX, gen_xxx_ptr, gen_helper_vfmin_d)
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TRANS(vfmaxa_s, LSX, gen_vvv_ptr, gen_helper_vfmaxa_s)
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TRANS(vfmaxa_d, LSX, gen_vvv_ptr, gen_helper_vfmaxa_d)
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TRANS(vfmina_s, LSX, gen_vvv_ptr, gen_helper_vfmina_s)
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TRANS(vfmina_d, LSX, gen_vvv_ptr, gen_helper_vfmina_d)
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TRANS(xvfmaxa_s, LASX, gen_xxx_ptr, gen_helper_vfmaxa_s)
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TRANS(xvfmaxa_d, LASX, gen_xxx_ptr, gen_helper_vfmaxa_d)
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TRANS(xvfmina_s, LASX, gen_xxx_ptr, gen_helper_vfmina_s)
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TRANS(xvfmina_d, LASX, gen_xxx_ptr, gen_helper_vfmina_d)
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TRANS(vflogb_s, LSX, gen_vv_ptr, gen_helper_vflogb_s)
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TRANS(vflogb_d, LSX, gen_vv_ptr, gen_helper_vflogb_d)
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TRANS(xvflogb_s, LASX, gen_xx_ptr, gen_helper_vflogb_s)
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TRANS(xvflogb_d, LASX, gen_xx_ptr, gen_helper_vflogb_d)
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TRANS(vfclass_s, LSX, gen_vv_ptr, gen_helper_vfclass_s)
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TRANS(vfclass_d, LSX, gen_vv_ptr, gen_helper_vfclass_d)
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TRANS(xvfclass_s, LASX, gen_xx_ptr, gen_helper_vfclass_s)
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TRANS(xvfclass_d, LASX, gen_xx_ptr, gen_helper_vfclass_d)
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TRANS(vfsqrt_s, LSX, gen_vv_ptr, gen_helper_vfsqrt_s)
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TRANS(vfsqrt_d, LSX, gen_vv_ptr, gen_helper_vfsqrt_d)
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@ -4345,6 +4390,12 @@ TRANS(vfrecip_s, LSX, gen_vv_ptr, gen_helper_vfrecip_s)
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TRANS(vfrecip_d, LSX, gen_vv_ptr, gen_helper_vfrecip_d)
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TRANS(vfrsqrt_s, LSX, gen_vv_ptr, gen_helper_vfrsqrt_s)
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TRANS(vfrsqrt_d, LSX, gen_vv_ptr, gen_helper_vfrsqrt_d)
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TRANS(xvfsqrt_s, LASX, gen_xx_ptr, gen_helper_vfsqrt_s)
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TRANS(xvfsqrt_d, LASX, gen_xx_ptr, gen_helper_vfsqrt_d)
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TRANS(xvfrecip_s, LASX, gen_xx_ptr, gen_helper_vfrecip_s)
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TRANS(xvfrecip_d, LASX, gen_xx_ptr, gen_helper_vfrecip_d)
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TRANS(xvfrsqrt_s, LASX, gen_xx_ptr, gen_helper_vfrsqrt_s)
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TRANS(xvfrsqrt_d, LASX, gen_xx_ptr, gen_helper_vfrsqrt_d)
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TRANS(vfcvtl_s_h, LSX, gen_vv_ptr, gen_helper_vfcvtl_s_h)
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TRANS(vfcvth_s_h, LSX, gen_vv_ptr, gen_helper_vfcvth_s_h)
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@ -1816,6 +1816,47 @@ xvfrstp_h 0111 01010010 10111 ..... ..... ..... @vvv
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xvfrstpi_b 0111 01101001 10100 ..... ..... ..... @vv_ui5
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xvfrstpi_h 0111 01101001 10101 ..... ..... ..... @vv_ui5
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xvfadd_s 0111 01010011 00001 ..... ..... ..... @vvv
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xvfadd_d 0111 01010011 00010 ..... ..... ..... @vvv
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xvfsub_s 0111 01010011 00101 ..... ..... ..... @vvv
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xvfsub_d 0111 01010011 00110 ..... ..... ..... @vvv
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xvfmul_s 0111 01010011 10001 ..... ..... ..... @vvv
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xvfmul_d 0111 01010011 10010 ..... ..... ..... @vvv
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xvfdiv_s 0111 01010011 10101 ..... ..... ..... @vvv
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xvfdiv_d 0111 01010011 10110 ..... ..... ..... @vvv
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xvfmadd_s 0000 10100001 ..... ..... ..... ..... @vvvv
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xvfmadd_d 0000 10100010 ..... ..... ..... ..... @vvvv
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xvfmsub_s 0000 10100101 ..... ..... ..... ..... @vvvv
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xvfmsub_d 0000 10100110 ..... ..... ..... ..... @vvvv
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xvfnmadd_s 0000 10101001 ..... ..... ..... ..... @vvvv
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xvfnmadd_d 0000 10101010 ..... ..... ..... ..... @vvvv
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xvfnmsub_s 0000 10101101 ..... ..... ..... ..... @vvvv
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xvfnmsub_d 0000 10101110 ..... ..... ..... ..... @vvvv
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xvfmax_s 0111 01010011 11001 ..... ..... ..... @vvv
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xvfmax_d 0111 01010011 11010 ..... ..... ..... @vvv
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xvfmin_s 0111 01010011 11101 ..... ..... ..... @vvv
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xvfmin_d 0111 01010011 11110 ..... ..... ..... @vvv
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xvfmaxa_s 0111 01010100 00001 ..... ..... ..... @vvv
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xvfmaxa_d 0111 01010100 00010 ..... ..... ..... @vvv
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xvfmina_s 0111 01010100 00101 ..... ..... ..... @vvv
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xvfmina_d 0111 01010100 00110 ..... ..... ..... @vvv
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xvflogb_s 0111 01101001 11001 10001 ..... ..... @vv
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xvflogb_d 0111 01101001 11001 10010 ..... ..... @vv
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xvfclass_s 0111 01101001 11001 10101 ..... ..... @vv
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xvfclass_d 0111 01101001 11001 10110 ..... ..... @vv
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xvfsqrt_s 0111 01101001 11001 11001 ..... ..... @vv
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xvfsqrt_d 0111 01101001 11001 11010 ..... ..... @vv
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xvfrecip_s 0111 01101001 11001 11101 ..... ..... @vv
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xvfrecip_d 0111 01101001 11001 11110 ..... ..... @vv
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xvfrsqrt_s 0111 01101001 11010 00001 ..... ..... @vv
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xvfrsqrt_d 0111 01101001 11010 00010 ..... ..... @vv
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xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
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xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
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xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
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@ -2452,9 +2452,10 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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int oprsz = simd_oprsz(desc); \
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\
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vec_clear_cause(env); \
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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for (i = 0; i < oprsz / (BIT / 8); i++) { \
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Vd->E(i) = FN(Vj->E(i), Vk->E(i), &env->fp_status); \
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vec_update_fcsr0(env, GETPC()); \
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} \
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@ -2486,9 +2487,10 @@ void HELPER(NAME)(void *vd, void *vj, void *vk, void *va, \
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VReg *Vj = (VReg *)vj; \
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VReg *Vk = (VReg *)vk; \
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VReg *Va = (VReg *)va; \
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int oprsz = simd_oprsz(desc); \
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\
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vec_clear_cause(env); \
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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for (i = 0; i < oprsz / (BIT / 8); i++) { \
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Vd->E(i) = FN(Vj->E(i), Vk->E(i), Va->E(i), flags, &env->fp_status); \
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vec_update_fcsr0(env, GETPC()); \
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} \
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@ -2512,9 +2514,10 @@ void HELPER(NAME)(void *vd, void *vj, \
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int i; \
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VReg *Vd = (VReg *)vd; \
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VReg *Vj = (VReg *)vj; \
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int oprsz = simd_oprsz(desc); \
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\
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vec_clear_cause(env); \
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for (i = 0; i < LSX_LEN/BIT; i++) { \
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for (i = 0; i < oprsz / (BIT / 8); i++) { \
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Vd->E(i) = FN(env, Vj->E(i)); \
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} \
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}
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@ -2544,8 +2547,9 @@ void HELPER(NAME)(void *vd, void *vj, \
|
||||
int i; \
|
||||
VReg *Vd = (VReg *)vd; \
|
||||
VReg *Vj = (VReg *)vj; \
|
||||
int oprsz = simd_oprsz(desc); \
|
||||
\
|
||||
for (i = 0; i < LSX_LEN/BIT; i++) { \
|
||||
for (i = 0; i < oprsz / (BIT / 8); i++) { \
|
||||
Vd->E(i) = FN(env, Vj->E(i)); \
|
||||
} \
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user