target-i386: Implement XSAVEOPT
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
19dc85dba2
commit
c9cfe8f9fb
@ -366,7 +366,9 @@ static const char *cpuid_6_feature_name[] = {
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#define TCG_7_0_ECX_FEATURES 0
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#define TCG_APM_FEATURES 0
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#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
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#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
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/* missing:
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CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
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typedef struct FeatureWordInfo {
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const char **feat_names;
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@ -440,7 +442,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.cpuid_eax = 0xd,
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.cpuid_needs_ecx = true, .cpuid_ecx = 1,
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.cpuid_reg = R_EAX,
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.tcg_features = 0,
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.tcg_features = TCG_XSAVE_FEATURES,
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},
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[FEAT_6_EAX] = {
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.feat_names = cpuid_6_feature_name,
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@ -1197,9 +1197,9 @@ static uint64_t get_xinuse(CPUX86State *env)
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return -1;
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}
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void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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static void do_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm,
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uint64_t inuse, uint64_t opt, uintptr_t ra)
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{
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uintptr_t ra = GETPC();
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uint64_t old_bv, new_bv;
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/* The OS must have enabled XSAVE. */
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@ -1214,21 +1214,36 @@ void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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/* Never save anything not enabled by XCR0. */
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rfbm &= env->xcr0;
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opt &= rfbm;
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if (rfbm & XSTATE_FP) {
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if (opt & XSTATE_FP) {
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do_xsave_fpu(env, ptr, ra);
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}
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if (rfbm & XSTATE_SSE) {
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/* Note that saving MXCSR is not suppressed by XSAVEOPT. */
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do_xsave_mxcsr(env, ptr, ra);
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}
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if (opt & XSTATE_SSE) {
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do_xsave_sse(env, ptr, ra);
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}
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/* Update the XSTATE_BV field. */
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old_bv = cpu_ldq_data_ra(env, ptr + 512, ra);
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new_bv = (old_bv & ~rfbm) | (get_xinuse(env) & rfbm);
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new_bv = (old_bv & ~rfbm) | (inuse & rfbm);
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cpu_stq_data_ra(env, ptr + 512, new_bv, ra);
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}
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void helper_xsave(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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{
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do_xsave(env, ptr, rfbm, get_xinuse(env), -1, GETPC());
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}
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void helper_xsaveopt(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
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{
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uint64_t inuse = get_xinuse(env);
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do_xsave(env, ptr, rfbm, inuse, inuse, GETPC());
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}
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static void do_xrstor_fpu(CPUX86State *env, target_ulong ptr, uintptr_t ra)
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{
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int i, fpus, fptag;
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@ -1369,8 +1384,10 @@ uint64_t helper_xgetbv(CPUX86State *env, uint32_t ecx)
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case 0:
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return env->xcr0;
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case 1:
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/* FIXME: #GP if !CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2]. */
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return env->xcr0 & get_xinuse(env);
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if (env->features[FEAT_XSAVE] & CPUID_XSAVE_XGETBV1) {
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return env->xcr0 & get_xinuse(env);
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}
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break;
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}
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raise_exception_ra(env, EXCP0D_GPF, GETPC());
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}
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@ -188,6 +188,7 @@ DEF_HELPER_3(frstor, void, env, tl, int)
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DEF_HELPER_FLAGS_2(fxsave, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_2(fxrstor, TCG_CALL_NO_WG, void, env, tl)
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DEF_HELPER_FLAGS_3(xsave, TCG_CALL_NO_WG, void, env, tl, i64)
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DEF_HELPER_FLAGS_3(xsaveopt, TCG_CALL_NO_WG, void, env, tl, i64)
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DEF_HELPER_FLAGS_3(xrstor, TCG_CALL_NO_WG, void, env, tl, i64)
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DEF_HELPER_FLAGS_2(xgetbv, TCG_CALL_NO_WG, i64, env, i32)
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DEF_HELPER_FLAGS_3(xsetbv, TCG_CALL_NO_WG, void, env, i32, i64)
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@ -127,6 +127,7 @@ typedef struct DisasContext {
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int cpuid_ext2_features;
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int cpuid_ext3_features;
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int cpuid_7_0_ebx_features;
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int cpuid_xsave_features;
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} DisasContext;
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static void gen_eob(DisasContext *s);
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@ -7634,7 +7635,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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gen_helper_xrstor(cpu_env, cpu_A0, cpu_tmp1_i64);
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break;
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CASE_MEM_OP(6): /* clwb */
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CASE_MEM_OP(6): /* xsaveopt / clwb */
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if (prefixes & PREFIX_LOCK) {
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goto illegal_op;
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}
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@ -7644,9 +7645,19 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
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goto illegal_op;
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}
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gen_nop_modrm(env, s, modrm);
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break;
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} else {
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/* xsaveopt */
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if ((s->cpuid_ext_features & CPUID_EXT_XSAVE) == 0
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|| (s->cpuid_xsave_features & CPUID_XSAVE_XSAVEOPT) == 0
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|| (prefixes & (PREFIX_REPZ | PREFIX_REPNZ))) {
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goto illegal_op;
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}
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gen_lea_modrm(env, s, modrm);
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tcg_gen_concat_tl_i64(cpu_tmp1_i64, cpu_regs[R_EAX],
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cpu_regs[R_EDX]);
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gen_helper_xsaveopt(cpu_env, cpu_A0, cpu_tmp1_i64);
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}
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goto illegal_op;
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break;
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CASE_MEM_OP(7): /* clflush / clflushopt */
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if (prefixes & PREFIX_LOCK) {
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@ -7868,6 +7879,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
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dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
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dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
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dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
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dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
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#ifdef TARGET_X86_64
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dc->lma = (flags >> HF_LMA_SHIFT) & 1;
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dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
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