ppc patch queue for 2023-03-03:
This queue includes a stub implementation for the dcblc instruction to avoid an illegal instrunction exception when using u-boot with mpc85xx. It also includes a PHB fix with user-created pnv-phb devices and Skiboot. -----BEGIN PGP SIGNATURE----- iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZAJllhYcZGFuaWVsaGI0 MTNAZ21haWwuY29tAAoJEDzZypbeAzFk02YA/2YnJl0aRw6hgiayI2rLbcwQcVfp oGAhh4QmqFL2UJw2AQDra0kh9sxBSEcqhltNnOa08tBnHPts3W/A8nmFtCd4Cw== =VRNM -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu into staging ppc patch queue for 2023-03-03: This queue includes a stub implementation for the dcblc instruction to avoid an illegal instrunction exception when using u-boot with mpc85xx. It also includes a PHB fix with user-created pnv-phb devices and Skiboot. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZAJllhYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFk02YA/2YnJl0aRw6hgiayI2rLbcwQcVfp # oGAhh4QmqFL2UJw2AQDra0kh9sxBSEcqhltNnOa08tBnHPts3W/A8nmFtCd4Cw== # =VRNM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 21:24:38 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu: pnv_phb4_pec: Simplify/align code to parent user-created PHBs pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file pnv_phb4_pec: Only export existing PHBs to the device tree pnv_phb4_pec: Keep track of instantiated PHBs target/ppc/translate: Add dummy implementation for dcblc instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
ca30a985e9
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@ -62,6 +62,15 @@ static bool pnv_parent_fixup(Object *parent, BusState *parent_bus,
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return true;
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}
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static Object *pnv_phb_user_get_parent(PnvChip *chip, PnvPHB *phb, Error **errp)
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{
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if (phb->version == 3) {
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return OBJECT(pnv_chip_add_phb(chip, phb));
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} else {
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return OBJECT(pnv_pec_add_phb(chip, phb, errp));
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}
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}
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/*
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* User created devices won't have the initial setup that default
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* devices have. This setup consists of assigning a parent device
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@ -79,7 +88,7 @@ static bool pnv_phb_user_device_init(PnvPHB *phb, Error **errp)
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return false;
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}
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parent = pnv_chip_add_phb(chip, phb, errp);
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parent = pnv_phb_user_get_parent(chip, phb, errp);
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if (!parent) {
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return false;
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}
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@ -112,9 +112,50 @@ static const MemoryRegionOps pnv_pec_pci_xscom_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
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int stack_no,
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Error **errp)
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PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
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{
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PnvPhb4PecState *pecs = NULL;
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int chip_id = phb->chip_id;
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int index = phb->phb_id;
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int i, j;
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if (phb->version == 4) {
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Pnv9Chip *chip9 = PNV9_CHIP(chip);
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pecs = chip9->pecs;
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} else if (phb->version == 5) {
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Pnv10Chip *chip10 = PNV10_CHIP(chip);
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pecs = chip10->pecs;
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} else {
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g_assert_not_reached();
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}
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for (i = 0; i < chip->num_pecs; i++) {
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/*
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* For each PEC, check the amount of phbs it supports
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* and see if the given phb4 index matches an index.
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*/
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PnvPhb4PecState *pec = &pecs[i];
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for (j = 0; j < pec->num_phbs; j++) {
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if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
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pec->phbs[j] = phb;
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phb->pec = pec;
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return pec;
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}
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}
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}
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error_setg(errp,
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"pnv-phb4 chip-id %d index %d didn't match any existing PEC",
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chip_id, index);
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return NULL;
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}
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static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
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int stack_no,
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Error **errp)
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{
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PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB));
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int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no);
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@ -128,8 +169,9 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec,
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&error_fatal);
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if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
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return;
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return NULL;
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}
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return phb;
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}
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static void pnv_pec_realize(DeviceState *dev, Error **errp)
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@ -148,8 +190,9 @@ static void pnv_pec_realize(DeviceState *dev, Error **errp)
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/* Create PHBs if running with defaults */
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if (defaults_enabled()) {
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g_assert(pec->num_phbs <= MAX_PHBS_PER_PEC);
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for (i = 0; i < pec->num_phbs; i++) {
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pnv_pec_default_phb_realize(pec, i, errp);
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pec->phbs[i] = pnv_pec_default_phb_realize(pec, i, errp);
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}
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}
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@ -197,9 +240,12 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
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pecc->compat_size)));
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for (i = 0; i < pec->num_phbs; i++) {
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int phb_id = pnv_phb4_pec_get_phb_id(pec, i);
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int stk_offset;
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if (!pec->phbs[i]) {
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continue;
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}
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name = g_strdup_printf("stack@%x", i);
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stk_offset = fdt_add_subnode(fdt, offset, name);
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_FDT(stk_offset);
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@ -207,7 +253,8 @@ static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt,
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_FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat,
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pecc->stk_compat_size)));
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_FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i)));
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_FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id)));
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_FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index",
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pec->phbs[i]->phb_id)));
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}
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return 0;
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70
hw/ppc/pnv.c
70
hw/ppc/pnv.c
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@ -284,73 +284,19 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
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g_free(reg);
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}
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static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
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Error **errp)
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{
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PnvPHB *phb_base = phb->phb_base;
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PnvPhb4PecState *pecs = NULL;
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int chip_id = phb->chip_id;
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int index = phb->phb_id;
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int i, j;
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if (phb_base->version == 4) {
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Pnv9Chip *chip9 = PNV9_CHIP(chip);
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pecs = chip9->pecs;
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} else if (phb_base->version == 5) {
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Pnv10Chip *chip10 = PNV10_CHIP(chip);
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pecs = chip10->pecs;
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} else {
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g_assert_not_reached();
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}
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for (i = 0; i < chip->num_pecs; i++) {
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/*
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* For each PEC, check the amount of phbs it supports
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* and see if the given phb4 index matches an index.
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*/
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PnvPhb4PecState *pec = &pecs[i];
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for (j = 0; j < pec->num_phbs; j++) {
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if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
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return pec;
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}
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}
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}
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error_setg(errp,
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"pnv-phb4 chip-id %d index %d didn't match any existing PEC",
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chip_id, index);
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return NULL;
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}
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/*
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* Adds a PnvPHB to the chip. Returns the parent obj of the
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* PHB which varies with each version (phb version 3 is parented
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* by the chip, version 4 and 5 are parented by the PEC
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* device).
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*
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* TODO: for version 3 we're still parenting the PHB with the
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* chip. We should parent with a (so far not implemented)
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* PHB3 PEC device.
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* Adds a PnvPHB to the chip on P8.
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* Implemented here, like for defaults PHBs
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*/
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Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
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PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
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{
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if (phb->version == 3) {
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Pnv8Chip *chip8 = PNV8_CHIP(chip);
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Pnv8Chip *chip8 = PNV8_CHIP(chip);
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phb->chip = chip;
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phb->chip = chip;
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chip8->phbs[chip8->num_phbs] = phb;
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chip8->num_phbs++;
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return OBJECT(chip);
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}
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phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp);
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return OBJECT(phb->pec);
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chip8->phbs[chip8->num_phbs] = phb;
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chip8->num_phbs++;
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return chip;
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}
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static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
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@ -157,6 +157,7 @@ struct PnvPHB4 {
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void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon);
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int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index);
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PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);
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void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb);
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extern const MemoryRegionOps pnv_phb4_xscom_ops;
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@ -185,6 +186,8 @@ struct PnvPhb4PecState {
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/* PHBs */
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uint32_t num_phbs;
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#define MAX_PHBS_PER_PEC 3
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PnvPHB *phbs[MAX_PHBS_PER_PEC];
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PnvChip *chip;
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};
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@ -100,7 +100,7 @@ struct PnvMachineState {
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};
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PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
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Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp);
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PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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@ -5253,6 +5253,14 @@ static void gen_dcbtls(DisasContext *ctx)
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tcg_temp_free(t0);
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}
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/* dcblc */
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static void gen_dcblc(DisasContext *ctx)
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{
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/*
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* interpreted as no-op
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*/
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}
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/* dcbz */
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static void gen_dcbz(DisasContext *ctx)
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{
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@ -6824,6 +6832,7 @@ GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
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GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
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GEN_HANDLER_E(dcblc, 0x1F, 0x06, 0x0c, 0x02000001, PPC_BOOKE, PPC2_BOOKE206),
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GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
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GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206),
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GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
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