target/loongarch: Add gdb support.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-42-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
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@ -1137,6 +1137,7 @@ F: include/hw/intc/loongarch_*.h
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F: hw/intc/loongarch_*.c
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F: hw/intc/loongarch_*.c
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F: include/hw/pci-host/ls7a.h
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F: include/hw/pci-host/ls7a.h
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F: hw/rtc/ls7a_rtc.c
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F: hw/rtc/ls7a_rtc.c
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F: gdb-xml/loongarch*.xml
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M68K Machines
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M68K Machines
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-------------
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-------------
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@ -1,3 +1,4 @@
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TARGET_ARCH=loongarch64
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TARGET_ARCH=loongarch64
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TARGET_BASE_ARCH=loongarch
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TARGET_BASE_ARCH=loongarch
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TARGET_SUPPORTS_MTTCG=y
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TARGET_SUPPORTS_MTTCG=y
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TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu64.xml
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44
gdb-xml/loongarch-base64.xml
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44
gdb-xml/loongarch-base64.xml
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@ -0,0 +1,44 @@
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<?xml version="1.0"?>
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<!-- Copyright (C) 2021 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.base">
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<reg name="r0" bitsize="64" type="uint64" group="general"/>
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<reg name="r1" bitsize="64" type="uint64" group="general"/>
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<reg name="r2" bitsize="64" type="uint64" group="general"/>
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<reg name="r3" bitsize="64" type="uint64" group="general"/>
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<reg name="r4" bitsize="64" type="uint64" group="general"/>
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<reg name="r5" bitsize="64" type="uint64" group="general"/>
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<reg name="r6" bitsize="64" type="uint64" group="general"/>
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<reg name="r7" bitsize="64" type="uint64" group="general"/>
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<reg name="r8" bitsize="64" type="uint64" group="general"/>
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<reg name="r9" bitsize="64" type="uint64" group="general"/>
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<reg name="r10" bitsize="64" type="uint64" group="general"/>
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<reg name="r11" bitsize="64" type="uint64" group="general"/>
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<reg name="r12" bitsize="64" type="uint64" group="general"/>
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<reg name="r13" bitsize="64" type="uint64" group="general"/>
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<reg name="r14" bitsize="64" type="uint64" group="general"/>
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<reg name="r15" bitsize="64" type="uint64" group="general"/>
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<reg name="r16" bitsize="64" type="uint64" group="general"/>
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<reg name="r17" bitsize="64" type="uint64" group="general"/>
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<reg name="r18" bitsize="64" type="uint64" group="general"/>
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<reg name="r19" bitsize="64" type="uint64" group="general"/>
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<reg name="r20" bitsize="64" type="uint64" group="general"/>
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<reg name="r21" bitsize="64" type="uint64" group="general"/>
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<reg name="r22" bitsize="64" type="uint64" group="general"/>
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<reg name="r23" bitsize="64" type="uint64" group="general"/>
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<reg name="r24" bitsize="64" type="uint64" group="general"/>
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<reg name="r25" bitsize="64" type="uint64" group="general"/>
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<reg name="r26" bitsize="64" type="uint64" group="general"/>
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<reg name="r27" bitsize="64" type="uint64" group="general"/>
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<reg name="r28" bitsize="64" type="uint64" group="general"/>
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<reg name="r29" bitsize="64" type="uint64" group="general"/>
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<reg name="r30" bitsize="64" type="uint64" group="general"/>
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<reg name="r31" bitsize="64" type="uint64" group="general"/>
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<reg name="pc" bitsize="64" type="code_ptr" group="general"/>
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<reg name="badvaddr" bitsize="64" type="code_ptr" group="general"/>
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</feature>
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57
gdb-xml/loongarch-fpu64.xml
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57
gdb-xml/loongarch-fpu64.xml
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<?xml version="1.0"?>
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<!-- Copyright (C) 2021 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.loongarch.fpu">
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<union id="fpu64type">
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<field name="f" type="ieee_single"/>
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<field name="d" type="ieee_double"/>
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</union>
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<reg name="f0" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f1" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f2" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f3" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f4" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f5" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f6" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f7" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f8" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f9" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f10" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f11" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f12" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f13" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f14" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f15" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f16" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f17" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f18" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f19" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f20" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f21" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f22" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f23" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f24" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f25" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f26" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f27" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f28" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f29" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f30" bitsize="64" type="fpu64type" group="float"/>
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<reg name="f31" bitsize="64" type="fpu64type" group="float"/>
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<reg name="fcc0" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc1" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc2" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc3" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc4" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc5" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc6" bitsize="8" type="uint8" group="float"/>
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<reg name="fcc7" bitsize="8" type="uint8" group="float"/>
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<reg name="fcsr" bitsize="32" type="uint32" group="float"/>
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</feature>
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@ -487,6 +487,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
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return;
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return;
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}
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}
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loongarch_cpu_register_gdb_regs_for_features(cs);
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cpu_reset(cs);
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cpu_reset(cs);
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qemu_init_vcpu(cs);
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qemu_init_vcpu(cs);
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@ -640,6 +642,13 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
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dc->vmsd = &vmstate_loongarch_cpu;
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dc->vmsd = &vmstate_loongarch_cpu;
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cc->sysemu_ops = &loongarch_sysemu_ops;
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cc->sysemu_ops = &loongarch_sysemu_ops;
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cc->disas_set_info = loongarch_cpu_disas_set_info;
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cc->disas_set_info = loongarch_cpu_disas_set_info;
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cc->gdb_read_register = loongarch_cpu_gdb_read_register;
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cc->gdb_write_register = loongarch_cpu_gdb_write_register;
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cc->disas_set_info = loongarch_cpu_disas_set_info;
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cc->gdb_num_core_regs = 34;
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cc->gdb_core_xml_file = "loongarch-base64.xml";
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cc->gdb_stop_before_watchpoint = true;
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#ifdef CONFIG_TCG
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#ifdef CONFIG_TCG
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cc->tcg_ops = &loongarch_tcg_ops;
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cc->tcg_ops = &loongarch_tcg_ops;
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#endif
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#endif
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81
target/loongarch/gdbstub.c
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81
target/loongarch/gdbstub.c
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/*
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* LOONGARCH gdb server stub
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*
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* SPDX-License-Identifier: LGPL-2.1+
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "internals.h"
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#include "exec/gdbstub.h"
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int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (0 <= n && n < 32) {
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return gdb_get_regl(mem_buf, env->gpr[n]);
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} else if (n == 32) {
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return gdb_get_regl(mem_buf, env->pc);
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} else if (n == 33) {
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return gdb_get_regl(mem_buf, env->badaddr);
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}
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return 0;
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}
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int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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target_ulong tmp = ldtul_p(mem_buf);
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int length = 0;
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if (0 <= n && n < 32) {
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env->gpr[n] = tmp;
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length = sizeof(target_ulong);
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} else if (n == 32) {
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env->pc = tmp;
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length = sizeof(target_ulong);
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}
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return length;
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}
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static int loongarch_gdb_get_fpu(CPULoongArchState *env,
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GByteArray *mem_buf, int n)
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{
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if (0 <= n && n < 32) {
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return gdb_get_reg64(mem_buf, env->fpr[n]);
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} else if (32 <= n && n < 40) {
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return gdb_get_reg8(mem_buf, env->cf[n - 32]);
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} else if (n == 40) {
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return gdb_get_reg32(mem_buf, env->fcsr0);
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}
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return 0;
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}
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static int loongarch_gdb_set_fpu(CPULoongArchState *env,
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uint8_t *mem_buf, int n)
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{
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int length = 0;
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if (0 <= n && n < 32) {
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env->fpr[n] = ldq_p(mem_buf);
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length = 8;
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} else if (32 <= n && n < 40) {
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env->cf[n - 32] = ldub_p(mem_buf);
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length = 1;
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} else if (n == 40) {
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env->fcsr0 = ldl_p(mem_buf);
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length = 4;
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}
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return length;
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}
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void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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gdb_register_coprocessor(cs, loongarch_gdb_get_fpu, loongarch_gdb_set_fpu,
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41, "loongarch-fpu64.xml", 0);
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}
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@ -49,4 +49,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
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int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
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void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
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#endif
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#endif
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@ -11,6 +11,7 @@ loongarch_tcg_ss.add(files(
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'fpu_helper.c',
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'fpu_helper.c',
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'op_helper.c',
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'op_helper.c',
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'translate.c',
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'translate.c',
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'gdbstub.c',
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))
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))
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loongarch_tcg_ss.add(zlib)
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loongarch_tcg_ss.add(zlib)
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