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target-mips: remove wrong checks for recip.fmt and rsqrt.fmt

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Instructions recip.{s|d} and rsqrt.{s|d} do not require 64-bit FPU neither
they require any particular mode for its FPU. This patch removes the checks
that may break a program that uses these instructions.

Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Petar Jovanovic 2015-08-26 14:12:20 +02:00 committed by Leon Alrae
parent 71f303cd24
commit ca6c7803d2
1 changed files with 2 additions and 4 deletions
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6
target-mips/translate.c
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@ -9290,7 +9290,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.s";
break;
case OPC_RECIP_S:
check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@ -9302,7 +9301,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.s";
break;
case OPC_RSQRT_S:
check_cop1x(ctx);
{
TCGv_i32 fp0 = tcg_temp_new_i32();
@ -9835,7 +9833,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "movn.d";
break;
case OPC_RECIP_D:
check_cp1_64bitmode(ctx);
check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();
@ -9847,7 +9845,7 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1,
opn = "recip.d";
break;
case OPC_RSQRT_D:
check_cp1_64bitmode(ctx);
check_cp1_registers(ctx, fs | fd);
{
TCGv_i64 fp0 = tcg_temp_new_i64();