Seventh RISC-V PR for 8.0
* Fix slli_uw decoding * Fix incorrect register name in disassembler for fmv,fabs,fneg instructions -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmQQFj4ACgkQIeENKd+X cFTDowgAhgganhgtSIKwCzQsfSh9P1KOnftmeRLtGQEC36YeJQc6CyqrgwOWCbBy +IEs/0/mXT0g70xaisQT2BKR9J6kevb1aHf790J13MmdFZmkpzTmS5SCQCHgUVjG SlFf2d2sIoLeBcZYorQSTZdRHjKG3KQ1y0dFWfaqYYwHVqko67fQhKTcqfu3Sn/l SKLeD3hz8iDc2Dh8HMls945rpQxATVTj5+/Fi8p0VL1194XK9dXRW4dpACZYJJEv T3u+tK5GUgLVXfxlXLxbk4yw4DtNofU0gaQNAfd2i6E9TImhstrvGDojt2pGrY8Y crLkAAxsOH8xNWYZdD5tcFrDZDrPvw== =oElO -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu into staging Seventh RISC-V PR for 8.0 * Fix slli_uw decoding * Fix incorrect register name in disassembler for fmv,fabs,fneg instructions # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmQQFj4ACgkQIeENKd+X # cFTDowgAhgganhgtSIKwCzQsfSh9P1KOnftmeRLtGQEC36YeJQc6CyqrgwOWCbBy # +IEs/0/mXT0g70xaisQT2BKR9J6kevb1aHf790J13MmdFZmkpzTmS5SCQCHgUVjG # SlFf2d2sIoLeBcZYorQSTZdRHjKG3KQ1y0dFWfaqYYwHVqko67fQhKTcqfu3Sn/l # SKLeD3hz8iDc2Dh8HMls945rpQxATVTj5+/Fi8p0VL1194XK9dXRW4dpACZYJJEv # T3u+tK5GUgLVXfxlXLxbk4yw4DtNofU0gaQNAfd2i6E9TImhstrvGDojt2pGrY8Y # crLkAAxsOH8xNWYZdD5tcFrDZDrPvw== # =oElO # -----END PGP SIGNATURE----- # gpg: Signature made Tue 14 Mar 2023 06:37:50 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20230314' of https://github.com/alistair23/qemu: Fix incorrect register name in disassembler for fmv,fabs,fneg instructions disas/riscv: Fix slli_uw decoding Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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caaf72fe47
@ -1014,6 +1014,7 @@ static const char rv_vreg_name_sym[32][4] = {
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#define rv_fmt_rd_offset "O\t0,o"
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#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
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#define rv_fmt_frd_rs1 "O\t3,1"
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#define rv_fmt_frd_frs1 "O\t3,4"
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#define rv_fmt_rd_frs1 "O\t0,4"
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#define rv_fmt_rd_frs1_frs2 "O\t0,4,5"
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#define rv_fmt_frd_frs1_frs2 "O\t3,4,5"
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@ -1580,15 +1581,15 @@ const rv_opcode_data opcode_data[] = {
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{ "snez", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
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{ "sltz", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "sgtz", rv_codec_r, rv_fmt_rd_rs2, NULL, 0, 0, 0 },
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{ "fmv.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fabs.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fneg.s", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fmv.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fabs.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fneg.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fmv.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fabs.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fneg.q", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "fmv.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fabs.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fneg.s", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fmv.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fabs.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fneg.d", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fmv.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fabs.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "fneg.q", rv_codec_r, rv_fmt_frd_frs1, NULL, 0, 0, 0 },
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{ "beqz", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
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{ "bnez", rv_codec_sb, rv_fmt_rs1_offset, NULL, 0, 0, 0 },
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{ "blez", rv_codec_sb, rv_fmt_rs2_offset, NULL, 0, 0, 0 },
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@ -1647,7 +1648,7 @@ const rv_opcode_data opcode_data[] = {
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{ "clzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "cpopw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },
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{ "slli.uw", rv_codec_i_sh5, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "slli.uw", rv_codec_i_sh6, rv_fmt_rd_rs1_imm, NULL, 0, 0, 0 },
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{ "add.uw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rolw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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{ "rorw", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 },
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@ -2617,10 +2618,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
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switch (((inst >> 12) & 0b111)) {
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case 0: op = rv_op_addiw; break;
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case 1:
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switch (((inst >> 25) & 0b1111111)) {
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switch (((inst >> 26) & 0b111111)) {
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case 0: op = rv_op_slliw; break;
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case 4: op = rv_op_slli_uw; break;
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case 48:
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case 2: op = rv_op_slli_uw; break;
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case 24:
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switch ((inst >> 20) & 0b11111) {
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case 0b00000: op = rv_op_clzw; break;
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case 0b00001: op = rv_op_ctzw; break;
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