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KVM: SVM: add migration support for nested TSC scaling

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Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
Message-Id: <20211101132300.192584-4-mlevitsk@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Maxim Levitsky 2021-11-01 15:23:00 +02:00 committed by Paolo Bonzini
parent 6aedeb650e
commit cabf9862e4
4 changed files with 46 additions and 0 deletions
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5
target/i386/cpu.c
View File

@ -5928,6 +5928,11 @@ static void x86_cpu_reset(DeviceState *dev)
}
x86_cpu_set_sgxlepubkeyhash(env);
if (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE) {
env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
}
#endif
}

4
target/i386/cpu.h
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@ -499,6 +499,9 @@ typedef enum X86Seg {
#define MSR_GSBASE 0xc0000101
#define MSR_KERNELGSBASE 0xc0000102
#define MSR_TSC_AUX 0xc0000103
#define MSR_AMD64_TSC_RATIO 0xc0000104
#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
#define MSR_VM_HSAVE_PA 0xc0010117
@ -1536,6 +1539,7 @@ typedef struct CPUX86State {
uint32_t tsx_ctrl;
uint64_t spec_ctrl;
uint64_t amd_tsc_scale_msr;
uint64_t virt_ssbd;
/* End of state preserved by INIT (dummy marker). */

15
target/i386/kvm/kvm.c
View File

@ -105,6 +105,7 @@ static bool has_msr_hv_reenlightenment;
static bool has_msr_xss;
static bool has_msr_umwait;
static bool has_msr_spec_ctrl;
static bool has_tsc_scale_msr;
static bool has_msr_tsx_ctrl;
static bool has_msr_virt_ssbd;
static bool has_msr_smi_count;
@ -2216,6 +2217,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_SPEC_CTRL:
has_msr_spec_ctrl = true;
break;
case MSR_AMD64_TSC_RATIO:
has_tsc_scale_msr = true;
break;
case MSR_IA32_TSX_CTRL:
has_msr_tsx_ctrl = true;
break;
@ -2972,6 +2976,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
if (has_tsc_scale_msr) {
kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
}
if (has_msr_tsx_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
}
@ -3377,6 +3385,10 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
if (has_tsc_scale_msr) {
kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
}
if (has_msr_tsx_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
}
@ -3788,6 +3800,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
case MSR_AMD64_TSC_RATIO:
env->amd_tsc_scale_msr = msrs[i].data;
break;
case MSR_IA32_TSX_CTRL:
env->tsx_ctrl = msrs[i].data;
break;

22
target/i386/machine.c
View File

@ -1280,6 +1280,27 @@ static const VMStateDescription vmstate_spec_ctrl = {
}
};
static bool amd_tsc_scale_msr_needed(void *opaque)
{
X86CPU *cpu = opaque;
CPUX86State *env = &cpu->env;
return (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE);
}
static const VMStateDescription amd_tsc_scale_msr_ctrl = {
.name = "cpu/amd_tsc_scale_msr",
.version_id = 1,
.minimum_version_id = 1,
.needed = amd_tsc_scale_msr_needed,
.fields = (VMStateField[]){
VMSTATE_UINT64(env.amd_tsc_scale_msr, X86CPU),
VMSTATE_END_OF_LIST()
}
};
static bool intel_pt_enable_needed(void *opaque)
{
X86CPU *cpu = opaque;
@ -1558,6 +1579,7 @@ const VMStateDescription vmstate_x86_cpu = {
&vmstate_pkru,
&vmstate_pkrs,
&vmstate_spec_ctrl,
&amd_tsc_scale_msr_ctrl,
&vmstate_mcg_ext_ctl,
&vmstate_msr_intel_pt,
&vmstate_msr_virt_ssbd,