KVM: SVM: add migration support for nested TSC scaling
Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com> Message-Id: <20211101132300.192584-4-mlevitsk@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -5928,6 +5928,11 @@ static void x86_cpu_reset(DeviceState *dev)
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}
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}
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x86_cpu_set_sgxlepubkeyhash(env);
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x86_cpu_set_sgxlepubkeyhash(env);
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if (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE) {
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env->amd_tsc_scale_msr = MSR_AMD64_TSC_RATIO_DEFAULT;
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}
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#endif
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#endif
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}
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}
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@ -499,6 +499,9 @@ typedef enum X86Seg {
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#define MSR_GSBASE 0xc0000101
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#define MSR_GSBASE 0xc0000101
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#define MSR_KERNELGSBASE 0xc0000102
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#define MSR_KERNELGSBASE 0xc0000102
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#define MSR_TSC_AUX 0xc0000103
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#define MSR_TSC_AUX 0xc0000103
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#define MSR_AMD64_TSC_RATIO 0xc0000104
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#define MSR_AMD64_TSC_RATIO_DEFAULT 0x100000000ULL
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#define MSR_VM_HSAVE_PA 0xc0010117
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#define MSR_VM_HSAVE_PA 0xc0010117
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@ -1536,6 +1539,7 @@ typedef struct CPUX86State {
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uint32_t tsx_ctrl;
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uint32_t tsx_ctrl;
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uint64_t spec_ctrl;
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uint64_t spec_ctrl;
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uint64_t amd_tsc_scale_msr;
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uint64_t virt_ssbd;
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uint64_t virt_ssbd;
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/* End of state preserved by INIT (dummy marker). */
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/* End of state preserved by INIT (dummy marker). */
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@ -105,6 +105,7 @@ static bool has_msr_hv_reenlightenment;
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static bool has_msr_xss;
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static bool has_msr_xss;
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static bool has_msr_umwait;
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static bool has_msr_umwait;
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static bool has_msr_spec_ctrl;
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static bool has_msr_spec_ctrl;
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static bool has_tsc_scale_msr;
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static bool has_msr_tsx_ctrl;
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static bool has_msr_tsx_ctrl;
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static bool has_msr_virt_ssbd;
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static bool has_msr_virt_ssbd;
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static bool has_msr_smi_count;
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static bool has_msr_smi_count;
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@ -2216,6 +2217,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case MSR_IA32_SPEC_CTRL:
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case MSR_IA32_SPEC_CTRL:
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has_msr_spec_ctrl = true;
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has_msr_spec_ctrl = true;
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break;
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break;
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case MSR_AMD64_TSC_RATIO:
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has_tsc_scale_msr = true;
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break;
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case MSR_IA32_TSX_CTRL:
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case MSR_IA32_TSX_CTRL:
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has_msr_tsx_ctrl = true;
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has_msr_tsx_ctrl = true;
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break;
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break;
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@ -2972,6 +2976,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_spec_ctrl) {
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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}
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}
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if (has_tsc_scale_msr) {
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kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
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}
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if (has_msr_tsx_ctrl) {
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if (has_msr_tsx_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
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kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
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}
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}
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@ -3377,6 +3385,10 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_spec_ctrl) {
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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}
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}
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if (has_tsc_scale_msr) {
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kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
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}
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if (has_msr_tsx_ctrl) {
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if (has_msr_tsx_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
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kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
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}
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}
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@ -3788,6 +3800,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_SPEC_CTRL:
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case MSR_IA32_SPEC_CTRL:
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env->spec_ctrl = msrs[i].data;
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env->spec_ctrl = msrs[i].data;
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break;
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break;
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case MSR_AMD64_TSC_RATIO:
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env->amd_tsc_scale_msr = msrs[i].data;
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break;
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case MSR_IA32_TSX_CTRL:
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case MSR_IA32_TSX_CTRL:
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env->tsx_ctrl = msrs[i].data;
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env->tsx_ctrl = msrs[i].data;
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break;
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break;
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@ -1280,6 +1280,27 @@ static const VMStateDescription vmstate_spec_ctrl = {
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}
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}
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};
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};
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static bool amd_tsc_scale_msr_needed(void *opaque)
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{
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X86CPU *cpu = opaque;
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CPUX86State *env = &cpu->env;
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return (env->features[FEAT_SVM] & CPUID_SVM_TSCSCALE);
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}
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static const VMStateDescription amd_tsc_scale_msr_ctrl = {
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.name = "cpu/amd_tsc_scale_msr",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = amd_tsc_scale_msr_needed,
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.fields = (VMStateField[]){
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VMSTATE_UINT64(env.amd_tsc_scale_msr, X86CPU),
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VMSTATE_END_OF_LIST()
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}
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};
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static bool intel_pt_enable_needed(void *opaque)
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static bool intel_pt_enable_needed(void *opaque)
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{
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{
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X86CPU *cpu = opaque;
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X86CPU *cpu = opaque;
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@ -1558,6 +1579,7 @@ const VMStateDescription vmstate_x86_cpu = {
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&vmstate_pkru,
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&vmstate_pkru,
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&vmstate_pkrs,
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&vmstate_pkrs,
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&vmstate_spec_ctrl,
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&vmstate_spec_ctrl,
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&amd_tsc_scale_msr_ctrl,
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&vmstate_mcg_ext_ctl,
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&vmstate_mcg_ext_ctl,
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&vmstate_msr_intel_pt,
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&vmstate_msr_intel_pt,
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&vmstate_msr_virt_ssbd,
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&vmstate_msr_virt_ssbd,
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