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target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions

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PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.

ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
exception and External EBB exception. They are being added as
POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.

PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
occurred and trigger the appropriate exception. Both exceptions are
doing the same thing in this first implementation: clear BESCR_GE and
enter the branch with env->nip retrieved from SPR_EBBHR.

The checks being done by the interrupt code are msr_pr and BESCR_GE
states. All other checks (EBB facility check, BESCR_PME bit, specific
bits related to the event type) must be done beforehand.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220225101140.1054160-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Daniel Henrique Barboza 2022-03-02 06:51:36 +01:00 committed by Cédric Le Goater
parent adc4eda103
commit cb76bbc43f
3 changed files with 41 additions and 1 deletions
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5
target/ppc/cpu.h
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@ -127,8 +127,10 @@ enum {
/* ISA 3.00 additions */
POWERPC_EXCP_HVIRT = 101,
POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
/* EOL */
POWERPC_EXCP_NB = 103,
POWERPC_EXCP_NB = 105,
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
@ -2434,6 +2436,7 @@ enum {
PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
PPC_INTERRUPT_EBB, /* Event-based Branch exception */
};
/* Processor Compatibility mask (PCR) */

4
target/ppc/cpu_init.c
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@ -2060,6 +2060,10 @@ static void init_excp_POWER8(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
/* Userland exceptions without vector value in PowerISA v3.1 */
env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
#endif
}

33
target/ppc/excp_helper.c
View File

@ -1554,6 +1554,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
env->spr[SPR_BESCR] &= ~BESCR_GE;
/*
* Save NIP for rfebb insn in SPR_EBBRR. Next nip is
* stored in the EBB Handler SPR_EBBHR.
*/
env->spr[SPR_EBBRR] = env->nip;
powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
/*
* This exception is handled in userspace. No need to proceed.
*/
return;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
@ -1797,6 +1812,24 @@ static void ppc_hw_interrupt(CPUPPCState *env)
powerpc_excp(cpu, POWERPC_EXCP_THERM);
return;
}
/* EBB exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) {
/*
* EBB exception must be taken in problem state and
* with BESCR_GE set.
*/
if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
if (env->spr[SPR_BESCR] & BESCR_PMEO) {
powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB);
} else if (env->spr[SPR_BESCR] & BESCR_EEO) {
powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB);
}
return;
}
}
}
if (env->resume_as_sreset) {