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MIPS queue for December 16th, 2019

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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into staging

MIPS queue for December 16th, 2019

# gpg: Signature made Mon 16 Dec 2019 12:29:24 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-dec-16-2019:
  MAINTAINERS: Add a file to MIPS section
  MAINTAINERS: Add three files to Malta section
  MAINTAINERS: Adjust maintainership for Malta board
  MAINTAINERS: Adjust maintainership for Fulong 2E board
  MAINTAINERS: Add a section on UI translation
  hw/mips: Deprecate the r4k machine
  mips: fulong 2e: Renovate coding style
  mips: r4000: Renovate coding style
  mips: mipssim: Renovate coding style
  mips: malta: Renovate coding style
  mips: jazz: Renovate coding style

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-12-16 14:07:56 +00:00
commit cb88904a54
11 changed files with 299 additions and 247 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
MAINTAINERS
View File

@ -221,6 +221,7 @@ F: include/hw/intc/mips_gic.h
F: include/hw/mips/
F: include/hw/misc/mips_*
F: include/hw/timer/mips_gictimer.h
F: tests/acceptance/linux_ssh_mips_malta.py
F: tests/tcg/mips/
K: ^Subject:.*(?i)mips
@ -955,11 +956,15 @@ F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
Malta
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
R: Aurelien Jarno <aurelien@aurel32.net>
S: Maintained
F: hw/isa/piix4.c
F: hw/acpi/piix4.c
F: hw/mips/mips_malta.c
F: hw/mips/gt64xxx_pci.c
F: include/hw/southbridge/piix.h
F: tests/acceptance/linux_ssh_mips_malta.py
Mipssim
@ -972,12 +977,12 @@ F: hw/net/mipsnet.c
R4000
M: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
S: Obsolete
F: hw/mips/mips_r4k.c
Fulong 2E
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@ -2715,6 +2720,10 @@ M: Daniel P. Berrange <berrange@redhat.com>
S: Odd Fixes
F: scripts/git-submodule.sh
UI translations
M: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
F: po/*.po
Sphinx documentation configuration and build machinery
M: Peter Maydell <peter.maydell@linaro.org>
S: Maintained

3
hw/display/jazz_led.c
View File

@ -205,8 +205,9 @@ static void jazz_led_update_display(void *opaque)
(s->segments & 0x80) ? color_segment : 0);
/* display led */
if (!(s->segments & 0x01))
if (!(s->segments & 0x01)) {
color_led = 0; /* black */
}
draw_horizontal_line(surface, 68, 50, 50, color_led);
draw_horizontal_line(surface, 69, 49, 51, color_led);
draw_horizontal_line(surface, 70, 48, 52, color_led);

12
hw/dma/rc4030.c
View File

@ -397,11 +397,12 @@ static void update_jazz_irq(rc4030State *s)
pending = s->isr_jazz & s->imr_jazz;
if (pending != 0)
if (pending != 0) {
qemu_irq_raise(s->jazz_bus_irq);
else
} else {
qemu_irq_lower(s->jazz_bus_irq);
}
}
static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
{
@ -588,7 +589,8 @@ static const VMStateDescription vmstate_rc4030 = {
}
};
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
int len, int is_write)
{
rc4030State *s = opaque;
hwaddr dma_addr;
@ -643,8 +645,8 @@ static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
struct rc4030DMAState *p;
int i;
s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
s = (rc4030_dma *)g_new0(rc4030_dma, n);
p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
for (i = 0; i < n; i++) {
p->opaque = opaque;
p->n = i;

13
hw/isa/vt82c686.c
View File

@ -27,7 +27,7 @@
#include "qemu/timer.h"
#include "exec/address-spaces.h"
//#define DEBUG_VT82C686B
/* #define DEBUG_VT82C686B */
#ifdef DEBUG_VT82C686B
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
@ -35,8 +35,7 @@
#define DPRINTF(fmt, ...)
#endif
typedef struct SuperIOConfig
{
typedef struct SuperIOConfig {
uint8_t config[0x100];
uint8_t index;
uint8_t data;
@ -102,7 +101,7 @@ static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
SuperIOConfig *superio_conf = opaque;
DPRINTF("superio_ioport_readb address 0x%x\n", addr);
return (superio_conf->config[superio_conf->index]);
return superio_conf->config[superio_conf->index];
}
static const MemoryRegionOps superio_ops = {
@ -470,8 +469,10 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
&vt82c->superio_conf, "superio", 2);
memory_region_set_enabled(&vt82c->superio, false);
/* The floppy also uses 0x3f0 and 0x3f1.
* But we do not emulate a floppy, so just set it here. */
/*
* The floppy also uses 0x3f0 and 0x3f1.
* But we do not emulate a floppy, so just set it here.
*/
memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
&vt82c->superio);
}

28
hw/mips/mips_jazz.c
View File

@ -52,8 +52,7 @@
#include "qemu/error-report.h"
#include "qemu/help_option.h"
enum jazz_model_e
{
enum jazz_model_e {
JAZZ_MAGNUM,
JAZZ_PICA61,
};
@ -90,16 +89,20 @@ static const MemoryRegionOps rtc_ops = {
static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
/*
* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed.
*/
return 0xff;
}
static void dma_dummy_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
/* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed. */
/*
* Nothing to do. That is only to ensure that
* the current DMA acknowledge cycle is completed.
*/
}
static const MemoryRegionOps dma_dummy_ops = {
@ -109,8 +112,8 @@ static const MemoryRegionOps dma_dummy_ops = {
};
#define MAGNUM_BIOS_SIZE_MAX 0x7e000
#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
#define MAGNUM_BIOS_SIZE \
(BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr,
vaddr addr, unsigned size,
MMUAccessType access_type,
@ -201,8 +204,9 @@ static void mips_jazz_init(MachineState *machine,
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
@ -229,7 +233,8 @@ static void mips_jazz_init(MachineState *machine,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops,
NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
@ -276,8 +281,9 @@ static void mips_jazz_init(MachineState *machine,
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
if (!nd->model) {
nd->model = g_strdup("dp83932");
}
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");

14
hw/mips/mips_malta.c
View File

@ -137,7 +137,8 @@ static void malta_fpga_update_display(void *opaque)
*/
#if defined(DEBUG)
# define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
# define logout(fmt, ...) \
fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
#else
# define logout(fmt, ...) ((void)0)
#endif
@ -359,7 +360,6 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
/* SWITCH Register */
case 0x00200:
/* ori a3, a3, low(ram_low_size) */
val = 0x00000000;
break;
@ -569,7 +569,7 @@ static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
MaltaFPGAState *s;
Chardev *chr;
s = (MaltaFPGAState *)g_malloc0(sizeof(MaltaFPGAState));
s = g_new0(MaltaFPGAState, 1);
memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
"malta-fpga", 0x100000);
@ -943,8 +943,10 @@ static void write_bootloader(uint8_t *base, int64_t run_addr,
stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */
/* Jump to kernel code */
stl_p(p++, 0x3c1f0000 | ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
stl_p(p++, 0x37ff0000 | (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
stl_p(p++, 0x3c1f0000 |
((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
stl_p(p++, 0x37ff0000 |
(kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */
stl_p(p++, 0x03e00009); /* jalr ra */
stl_p(p++, 0x00000000); /* nop */
@ -1242,7 +1244,7 @@ void mips_malta_init(MachineState *machine)
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
* emulate this feature.\
* emulate this feature.
*/
empty_slot_init(0, 0x20000000);

42
hw/mips/mips_r4k.c
View File

@ -57,11 +57,12 @@ static struct _loaderparams {
static void mips_qemu_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
if ((addr & 0xffff) == 0 && val == 42)
if ((addr & 0xffff) == 0 && val == 42) {
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
else if ((addr & 0xffff) == 4 && val == 42)
} else if ((addr & 0xffff) == 4 && val == 42) {
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
}
}
static uint64_t mips_qemu_read(void *opaque, hwaddr addr,
unsigned size)
@ -100,8 +101,9 @@ static int64_t load_kernel(void)
(uint64_t *)&kernel_high, big_endian,
EM_MIPS, 1, 0);
if (kernel_size >= 0) {
if ((entry & ~0x7fffffffULL) == 0x80000000)
if ((entry & ~0x7fffffffULL) == 0x80000000) {
entry = (int32_t)entry;
}
} else {
error_report("could not load kernel '%s': %s",
loaderparams.kernel_filename,
@ -115,7 +117,8 @@ static int64_t load_kernel(void)
if (loaderparams.initrd_filename) {
initrd_size = get_image_size(loaderparams.initrd_filename);
if (initrd_size > 0) {
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) & INITRD_PAGE_MASK;
initrd_offset = (kernel_high + ~INITRD_PAGE_MASK) &
INITRD_PAGE_MASK;
if (initrd_offset + initrd_size > ram_size) {
error_report("memory too small for initial ram disk '%s'",
loaderparams.initrd_filename);
@ -139,11 +142,13 @@ static int64_t load_kernel(void)
params_buf[1] = tswap32(0x12345678);
if (initrd_size > 0) {
snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
snprintf((char *)params_buf + 8, 256,
"rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
cpu_mips_phys_to_kseg0(NULL, initrd_offset),
initrd_size, loaderparams.kernel_cmdline);
} else {
snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
snprintf((char *)params_buf + 8, 256,
"%s", loaderparams.kernel_cmdline);
}
rom_add_blob_fixed("params", params_buf, params_size,
@ -207,15 +212,21 @@ void mips_r4k_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
memory_region_init_io(iomem, NULL, &mips_qemu_ops,
NULL, "mips-qemu", 0x10000);
memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets
preloaded we also initialize the hardware, since the BIOS wasn't
run. */
if (bios_name == NULL)
/*
* Try to load a BIOS image. If this fails, we continue regardless,
* but initialize the hardware ourselves. When a kernel gets
* preloaded we also initialize the hardware, since the BIOS wasn't
* run.
*/
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = get_image_size(filename);
@ -227,6 +238,7 @@ void mips_r4k_init(MachineState *machine)
#else
be = 0;
#endif
dinfo = drive_get(IF_PFLASH, 0, 0);
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE,
@ -235,7 +247,7 @@ void mips_r4k_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
} else if (dinfo != NULL) {
uint32_t mips_rom = 0x00400000;
if (!pflash_cfi01_register(0x1fc00000, "mips_r4k.bios", mips_rom,
blk_by_legacy_dinfo(dinfo),
@ -280,8 +292,9 @@ void mips_r4k_init(MachineState *machine)
isa_vga_init(isa_bus);
if (nd_table[0].used)
if (nd_table[0].used) {
isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
for (i = 0; i < MAX_IDE_BUS; i++)
@ -294,6 +307,7 @@ void mips_r4k_init(MachineState *machine)
static void mips_machine_init(MachineClass *mc)
{
mc->deprecation_reason = "use malta machine type instead";
mc->desc = "mips r4k platform";
mc->init = mips_r4k_init;
mc->block_default_type = IF_IDE;

12
hw/net/mipsnet.c
View File

@ -64,8 +64,9 @@ static void mipsnet_update_irq(MIPSnetState *s)
static int mipsnet_buffer_full(MIPSnetState *s)
{
if (s->rx_count >= MAX_ETH_FRAME_SIZE)
if (s->rx_count >= MAX_ETH_FRAME_SIZE) {
return 1;
}
return 0;
}
@ -73,18 +74,21 @@ static int mipsnet_can_receive(NetClientState *nc)
{
MIPSnetState *s = qemu_get_nic_opaque(nc);
if (s->busy)
if (s->busy) {
return 0;
}
return !mipsnet_buffer_full(s);
}
static ssize_t mipsnet_receive(NetClientState *nc, const uint8_t *buf, size_t size)
static ssize_t mipsnet_receive(NetClientState *nc,
const uint8_t *buf, size_t size)
{
MIPSnetState *s = qemu_get_nic_opaque(nc);
trace_mipsnet_receive(size);
if (!mipsnet_can_receive(nc))
if (!mipsnet_can_receive(nc)) {
return 0;
}
if (size >= sizeof(s->rx_buffer)) {
return 0;

22
hw/pci-host/bonito.c
View File

@ -14,7 +14,8 @@
* fulong 2e mini pc has a bonito north bridge.
*/
/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
/*
* what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
*
* devfn pci_slot<<3 + funno
* one pci bus can have 32 devices and each device can have 8 functions.
@ -49,7 +50,7 @@
#include "sysemu/runstate.h"
#include "exec/address-spaces.h"
//#define DEBUG_BONITO
/* #define DEBUG_BONITO */
#ifdef DEBUG_BONITO
#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
@ -180,12 +181,12 @@
#define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
#define PCI_ADDR(busno , devno , funno , regno) \
((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno))
((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \
(((funno) << 8) & 0x700) + (regno))
typedef struct BonitoState BonitoState;
typedef struct PCIBonitoState
{
typedef struct PCIBonitoState {
PCIDevice dev;
BonitoState *pcihost;
@ -239,7 +240,8 @@ static void bonito_writel(void *opaque, hwaddr addr,
saddr = addr >> 2;
DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr);
DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n",
addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
case BONITO_IODEVCFG:
@ -446,7 +448,8 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
cfgaddr = addr & 0xffff;
cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET;
idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
BONITO_PCICONF_IDSEL_OFFSET;
devno = ctz32(idsel);
funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
@ -618,7 +621,10 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
/* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */
/*
* Bonito North Bridge, built on FPGA,
* VENDOR_ID/DEVICE_ID are "undefined"
*/
pci_config_set_prog_interface(dev->config, 0x00);
/* set the north bridge register mapping */

5
qemu-deprecated.texi
View File

@ -261,6 +261,11 @@ The 'scsi-disk' device is deprecated. Users should use 'scsi-hd' or
@section System emulator machines
@subsection mips r4k platform (since 4.2)
This machine type is very old and unmaintained. Users should use the 'malta'
machine type instead.
@subsection pc-0.12, pc-0.13, pc-0.14 and pc-0.15 (since 4.0)
These machine types are very old and likely can not be used for live migration

6
tests/acceptance/linux_ssh_mips_malta.py
View File

@ -99,10 +99,12 @@ class LinuxSSH(Test):
def ssh_command(self, command, is_root=True):
self.ssh_logger.info(command)
result = self.ssh_session.cmd(command)
stdout_lines = [line.rstrip() for line in result.stdout_text.splitlines()]
stdout_lines = [line.rstrip() for line
in result.stdout_text.splitlines()]
for line in stdout_lines:
self.ssh_logger.info(line)
stderr_lines = [line.rstrip() for line in result.stderr_text.splitlines()]
stderr_lines = [line.rstrip() for line
in result.stderr_text.splitlines()]
for line in stderr_lines:
self.ssh_logger.warning(line)
return stdout_lines, stderr_lines