hw/block/nvme: add support for scatter gather lists
For now, support the Data Block, Segment and Last Segment descriptor
types.
See NVM Express 1.3d, Section 4.4 ("Scatter Gather List (SGL)").
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
This commit is contained in:
Klaus Jensen
parent
6e0ac3a03f
commit
cba0a8a344
329
hw/block/nvme.c
329
hw/block/nvme.c
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@ -413,13 +413,262 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
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return NVME_SUCCESS;
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}
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static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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uint64_t prp1, uint64_t prp2, DMADirection dir,
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/*
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* Map 'nsgld' data descriptors from 'segment'. The function will subtract the
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* number of bytes mapped in len.
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*/
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static uint16_t nvme_map_sgl_data(NvmeCtrl *n, QEMUSGList *qsg,
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QEMUIOVector *iov,
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NvmeSglDescriptor *segment, uint64_t nsgld,
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size_t *len, NvmeRequest *req)
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{
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dma_addr_t addr, trans_len;
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uint32_t dlen;
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uint16_t status;
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for (int i = 0; i < nsgld; i++) {
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uint8_t type = NVME_SGL_TYPE(segment[i].type);
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switch (type) {
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case NVME_SGL_DESCR_TYPE_DATA_BLOCK:
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break;
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case NVME_SGL_DESCR_TYPE_SEGMENT:
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case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
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return NVME_INVALID_NUM_SGL_DESCRS | NVME_DNR;
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default:
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return NVME_SGL_DESCR_TYPE_INVALID | NVME_DNR;
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}
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dlen = le32_to_cpu(segment[i].len);
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if (!dlen) {
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continue;
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}
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if (*len == 0) {
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/*
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* All data has been mapped, but the SGL contains additional
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* segments and/or descriptors. The controller might accept
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* ignoring the rest of the SGL.
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*/
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uint16_t sgls = le16_to_cpu(n->id_ctrl.sgls);
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if (sgls & NVME_CTRL_SGLS_EXCESS_LENGTH) {
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break;
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}
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trace_pci_nvme_err_invalid_sgl_excess_length(nvme_cid(req));
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return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
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}
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trans_len = MIN(*len, dlen);
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addr = le64_to_cpu(segment[i].addr);
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if (UINT64_MAX - addr < dlen) {
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return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
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}
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status = nvme_map_addr(n, qsg, iov, addr, trans_len);
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if (status) {
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return status;
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}
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*len -= trans_len;
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}
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return NVME_SUCCESS;
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}
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static uint16_t nvme_map_sgl(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
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NvmeSglDescriptor sgl, size_t len,
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NvmeRequest *req)
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{
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/*
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* Read the segment in chunks of 256 descriptors (one 4k page) to avoid
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* dynamically allocating a potentially huge SGL. The spec allows the SGL
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* to be larger (as in number of bytes required to describe the SGL
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* descriptors and segment chain) than the command transfer size, so it is
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* not bounded by MDTS.
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*/
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const int SEG_CHUNK_SIZE = 256;
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NvmeSglDescriptor segment[SEG_CHUNK_SIZE], *sgld, *last_sgld;
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uint64_t nsgld;
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uint32_t seg_len;
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uint16_t status;
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bool sgl_in_cmb = false;
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hwaddr addr;
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int ret;
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sgld = &sgl;
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addr = le64_to_cpu(sgl.addr);
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trace_pci_nvme_map_sgl(nvme_cid(req), NVME_SGL_TYPE(sgl.type), len);
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/*
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* If the entire transfer can be described with a single data block it can
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* be mapped directly.
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*/
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if (NVME_SGL_TYPE(sgl.type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
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status = nvme_map_sgl_data(n, qsg, iov, sgld, 1, &len, req);
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if (status) {
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goto unmap;
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}
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goto out;
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}
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/*
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* If the segment is located in the CMB, the submission queue of the
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* request must also reside there.
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*/
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if (nvme_addr_is_cmb(n, addr)) {
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if (!nvme_addr_is_cmb(n, req->sq->dma_addr)) {
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return NVME_INVALID_USE_OF_CMB | NVME_DNR;
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}
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sgl_in_cmb = true;
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}
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for (;;) {
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switch (NVME_SGL_TYPE(sgld->type)) {
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case NVME_SGL_DESCR_TYPE_SEGMENT:
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case NVME_SGL_DESCR_TYPE_LAST_SEGMENT:
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break;
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default:
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return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
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}
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seg_len = le32_to_cpu(sgld->len);
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/* check the length of the (Last) Segment descriptor */
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if (!seg_len || seg_len & 0xf) {
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return NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
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}
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if (UINT64_MAX - addr < seg_len) {
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return NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
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}
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nsgld = seg_len / sizeof(NvmeSglDescriptor);
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while (nsgld > SEG_CHUNK_SIZE) {
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if (nvme_addr_read(n, addr, segment, sizeof(segment))) {
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trace_pci_nvme_err_addr_read(addr);
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status = NVME_DATA_TRAS_ERROR;
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goto unmap;
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}
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status = nvme_map_sgl_data(n, qsg, iov, segment, SEG_CHUNK_SIZE,
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&len, req);
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if (status) {
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goto unmap;
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}
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nsgld -= SEG_CHUNK_SIZE;
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addr += SEG_CHUNK_SIZE * sizeof(NvmeSglDescriptor);
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}
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ret = nvme_addr_read(n, addr, segment, nsgld *
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sizeof(NvmeSglDescriptor));
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if (ret) {
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trace_pci_nvme_err_addr_read(addr);
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status = NVME_DATA_TRAS_ERROR;
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goto unmap;
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}
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last_sgld = &segment[nsgld - 1];
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/* if the segment ends with a Data Block, then we are done */
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if (NVME_SGL_TYPE(last_sgld->type) == NVME_SGL_DESCR_TYPE_DATA_BLOCK) {
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status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld, &len, req);
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if (status) {
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goto unmap;
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}
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goto out;
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}
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/*
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* If the last descriptor was not a Data Block, then the current
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* segment must not be a Last Segment.
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*/
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if (NVME_SGL_TYPE(sgld->type) == NVME_SGL_DESCR_TYPE_LAST_SEGMENT) {
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status = NVME_INVALID_SGL_SEG_DESCR | NVME_DNR;
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goto unmap;
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}
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sgld = last_sgld;
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addr = le64_to_cpu(sgld->addr);
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/*
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* Do not map the last descriptor; it will be a Segment or Last Segment
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* descriptor and is handled by the next iteration.
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*/
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status = nvme_map_sgl_data(n, qsg, iov, segment, nsgld - 1, &len, req);
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if (status) {
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goto unmap;
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}
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/*
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* If the next segment is in the CMB, make sure that the sgl was
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* already located there.
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*/
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if (sgl_in_cmb != nvme_addr_is_cmb(n, addr)) {
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status = NVME_INVALID_USE_OF_CMB | NVME_DNR;
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goto unmap;
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}
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}
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out:
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/* if there is any residual left in len, the SGL was too short */
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if (len) {
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status = NVME_DATA_SGL_LEN_INVALID | NVME_DNR;
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goto unmap;
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}
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return NVME_SUCCESS;
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unmap:
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if (iov->iov) {
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qemu_iovec_destroy(iov);
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}
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if (qsg->sg) {
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qemu_sglist_destroy(qsg);
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}
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return status;
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}
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static uint16_t nvme_map_dptr(NvmeCtrl *n, size_t len, NvmeRequest *req)
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{
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uint64_t prp1, prp2;
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switch (NVME_CMD_FLAGS_PSDT(req->cmd.flags)) {
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case NVME_PSDT_PRP:
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prp1 = le64_to_cpu(req->cmd.dptr.prp1);
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prp2 = le64_to_cpu(req->cmd.dptr.prp2);
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return nvme_map_prp(n, prp1, prp2, len, req);
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case NVME_PSDT_SGL_MPTR_CONTIGUOUS:
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case NVME_PSDT_SGL_MPTR_SGL:
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/* SGLs shall not be used for Admin commands in NVMe over PCIe */
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if (!req->sq->sqid) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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return nvme_map_sgl(n, &req->qsg, &req->iov, req->cmd.dptr.sgl, len,
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req);
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default:
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return NVME_INVALID_FIELD;
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}
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}
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static uint16_t nvme_dma(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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DMADirection dir, NvmeRequest *req)
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{
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uint16_t status = NVME_SUCCESS;
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status = nvme_map_prp(n, prp1, prp2, len, req);
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status = nvme_map_dptr(n, len, req);
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if (status) {
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return status;
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}
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@ -458,15 +707,6 @@ static uint16_t nvme_dma_prp(NvmeCtrl *n, uint8_t *ptr, uint32_t len,
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return status;
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}
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static uint16_t nvme_map_dptr(NvmeCtrl *n, size_t len, NvmeRequest *req)
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{
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NvmeCmd *cmd = &req->cmd;
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uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
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uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
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return nvme_map_prp(n, prp1, prp2, len, req);
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}
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static void nvme_post_cqes(void *opaque)
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{
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NvmeCQueue *cq = opaque;
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@ -929,10 +1169,7 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeRequest *req)
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static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
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uint64_t off, NvmeRequest *req)
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{
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NvmeCmd *cmd = &req->cmd;
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uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
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uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
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uint32_t nsid = le32_to_cpu(cmd->nsid);
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uint32_t nsid = le32_to_cpu(req->cmd.nsid);
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uint32_t trans_len;
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time_t current_ms;
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@ -981,17 +1218,14 @@ static uint16_t nvme_smart_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
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nvme_clear_events(n, NVME_AER_TYPE_SMART);
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}
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return nvme_dma_prp(n, (uint8_t *) &smart + off, trans_len, prp1, prp2,
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DMA_DIRECTION_FROM_DEVICE, req);
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return nvme_dma(n, (uint8_t *) &smart + off, trans_len,
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DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
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NvmeRequest *req)
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{
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uint32_t trans_len;
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NvmeCmd *cmd = &req->cmd;
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uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
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uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
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NvmeFwSlotInfoLog fw_log = {
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.afi = 0x1,
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};
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@ -1004,17 +1238,14 @@ static uint16_t nvme_fw_log_info(NvmeCtrl *n, uint32_t buf_len, uint64_t off,
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trans_len = MIN(sizeof(fw_log) - off, buf_len);
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return nvme_dma_prp(n, (uint8_t *) &fw_log + off, trans_len, prp1, prp2,
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DMA_DIRECTION_FROM_DEVICE, req);
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return nvme_dma(n, (uint8_t *) &fw_log + off, trans_len,
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DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
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uint64_t off, NvmeRequest *req)
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{
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uint32_t trans_len;
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NvmeCmd *cmd = &req->cmd;
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uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
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uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
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NvmeErrorLog errlog;
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if (!rae) {
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@ -1029,8 +1260,8 @@ static uint16_t nvme_error_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,
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trans_len = MIN(sizeof(errlog) - off, buf_len);
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return nvme_dma_prp(n, (uint8_t *)&errlog, trans_len, prp1, prp2,
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DMA_DIRECTION_FROM_DEVICE, req);
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return nvme_dma(n, (uint8_t *)&errlog, trans_len,
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DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_get_log(NvmeCtrl *n, NvmeRequest *req)
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@ -1190,14 +1421,10 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequest *req)
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static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req)
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{
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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uint64_t prp1 = le64_to_cpu(c->prp1);
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uint64_t prp2 = le64_to_cpu(c->prp2);
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trace_pci_nvme_identify_ctrl();
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return nvme_dma_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1,
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prp2, DMA_DIRECTION_FROM_DEVICE, req);
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return nvme_dma(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl),
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DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
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@ -1205,8 +1432,6 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
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NvmeNamespace *ns;
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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uint32_t nsid = le32_to_cpu(c->nsid);
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uint64_t prp1 = le64_to_cpu(c->prp1);
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uint64_t prp2 = le64_to_cpu(c->prp2);
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trace_pci_nvme_identify_ns(nsid);
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@ -1217,8 +1442,8 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req)
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ns = &n->namespaces[nsid - 1];
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return nvme_dma_prp(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns), prp1,
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prp2, DMA_DIRECTION_FROM_DEVICE, req);
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return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(ns->id_ns),
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DMA_DIRECTION_FROM_DEVICE, req);
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}
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static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
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@ -1226,8 +1451,6 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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static const int data_len = NVME_IDENTIFY_DATA_SIZE;
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uint32_t min_nsid = le32_to_cpu(c->nsid);
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uint64_t prp1 = le64_to_cpu(c->prp1);
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uint64_t prp2 = le64_to_cpu(c->prp2);
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uint32_t *list;
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uint16_t ret;
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int i, j = 0;
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@ -1254,8 +1477,8 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req)
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break;
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}
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}
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ret = nvme_dma_prp(n, (uint8_t *)list, data_len, prp1, prp2,
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DMA_DIRECTION_FROM_DEVICE, req);
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ret = nvme_dma(n, (uint8_t *)list, data_len, DMA_DIRECTION_FROM_DEVICE,
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req);
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g_free(list);
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return ret;
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}
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@ -1264,8 +1487,6 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
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{
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NvmeIdentify *c = (NvmeIdentify *)&req->cmd;
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uint32_t nsid = le32_to_cpu(c->nsid);
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uint64_t prp1 = le64_to_cpu(c->prp1);
|
||||
uint64_t prp2 = le64_to_cpu(c->prp2);
|
||||
|
||||
uint8_t list[NVME_IDENTIFY_DATA_SIZE];
|
||||
|
||||
|
|
@ -1297,8 +1518,8 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
|
|||
ns_descrs->uuid.hdr.nidl = NVME_NIDT_UUID_LEN;
|
||||
stl_be_p(&ns_descrs->uuid.v, nsid);
|
||||
|
||||
return nvme_dma_prp(n, list, NVME_IDENTIFY_DATA_SIZE, prp1, prp2,
|
||||
DMA_DIRECTION_FROM_DEVICE, req);
|
||||
return nvme_dma(n, list, NVME_IDENTIFY_DATA_SIZE,
|
||||
DMA_DIRECTION_FROM_DEVICE, req);
|
||||
}
|
||||
|
||||
static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req)
|
||||
|
|
@ -1369,14 +1590,10 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n)
|
|||
|
||||
static uint16_t nvme_get_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
|
||||
{
|
||||
NvmeCmd *cmd = &req->cmd;
|
||||
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
|
||||
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
|
||||
|
||||
uint64_t timestamp = nvme_get_timestamp(n);
|
||||
|
||||
return nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
|
||||
prp2, DMA_DIRECTION_FROM_DEVICE, req);
|
||||
return nvme_dma(n, (uint8_t *)×tamp, sizeof(timestamp),
|
||||
DMA_DIRECTION_FROM_DEVICE, req);
|
||||
}
|
||||
|
||||
static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeRequest *req)
|
||||
|
|
@ -1505,12 +1722,9 @@ static uint16_t nvme_set_feature_timestamp(NvmeCtrl *n, NvmeRequest *req)
|
|||
{
|
||||
uint16_t ret;
|
||||
uint64_t timestamp;
|
||||
NvmeCmd *cmd = &req->cmd;
|
||||
uint64_t prp1 = le64_to_cpu(cmd->dptr.prp1);
|
||||
uint64_t prp2 = le64_to_cpu(cmd->dptr.prp2);
|
||||
|
||||
ret = nvme_dma_prp(n, (uint8_t *)×tamp, sizeof(timestamp), prp1,
|
||||
prp2, DMA_DIRECTION_TO_DEVICE, req);
|
||||
ret = nvme_dma(n, (uint8_t *)×tamp, sizeof(timestamp),
|
||||
DMA_DIRECTION_TO_DEVICE, req);
|
||||
if (ret != NVME_SUCCESS) {
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -2437,6 +2651,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
|
|||
id->nn = cpu_to_le32(n->num_namespaces);
|
||||
id->oncs = cpu_to_le16(NVME_ONCS_WRITE_ZEROES | NVME_ONCS_TIMESTAMP |
|
||||
NVME_ONCS_FEATURES);
|
||||
id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN);
|
||||
|
||||
subnqn = g_strdup_printf("nqn.2019-08.org.qemu:%s", n->params.serial);
|
||||
strpadcpy((char *)id->subnqn, sizeof(id->subnqn), subnqn, '\0');
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@ pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=0x%"PRIx64" prp2
|
|||
pci_nvme_map_addr(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
|
||||
pci_nvme_map_addr_cmb(uint64_t addr, uint64_t len) "addr 0x%"PRIx64" len %"PRIu64""
|
||||
pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2, int num_prps) "trans_len %"PRIu64" len %"PRIu32" prp1 0x%"PRIx64" prp2 0x%"PRIx64" num_prps %d"
|
||||
pci_nvme_map_sgl(uint16_t cid, uint8_t typ, uint64_t len) "cid %"PRIu16" type 0x%"PRIx8" len %"PRIu64""
|
||||
pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
|
||||
pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
|
||||
pci_nvme_rw(uint16_t cid, const char *verb, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" '%s' nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
|
||||
|
|
@ -91,6 +92,9 @@ pci_nvme_err_addr_read(uint64_t addr) "addr 0x%"PRIx64""
|
|||
pci_nvme_err_addr_write(uint64_t addr) "addr 0x%"PRIx64""
|
||||
pci_nvme_err_cfs(void) "controller fatal status"
|
||||
pci_nvme_err_aio(uint16_t cid, const char *errname, uint16_t status) "cid %"PRIu16" err '%s' status 0x%"PRIx16""
|
||||
pci_nvme_err_invalid_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8""
|
||||
pci_nvme_err_invalid_num_sgld(uint16_t cid, uint8_t typ) "cid %"PRIu16" type 0x%"PRIx8""
|
||||
pci_nvme_err_invalid_sgl_excess_length(uint16_t cid) "cid %"PRIu16""
|
||||
pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size"
|
||||
pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or not page aligned: 0x%"PRIx64""
|
||||
pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"PRIx64""
|
||||
|
|
|
|||
|
|
@ -412,9 +412,9 @@ typedef union NvmeCmdDptr {
|
|||
} NvmeCmdDptr;
|
||||
|
||||
enum NvmePsdt {
|
||||
PSDT_PRP = 0x0,
|
||||
PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
|
||||
PSDT_SGL_MPTR_SGL = 0x2,
|
||||
NVME_PSDT_PRP = 0x0,
|
||||
NVME_PSDT_SGL_MPTR_CONTIGUOUS = 0x1,
|
||||
NVME_PSDT_SGL_MPTR_SGL = 0x2,
|
||||
};
|
||||
|
||||
typedef struct QEMU_PACKED NvmeCmd {
|
||||
|
|
|
|||
Loading…
Reference in New Issue