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Fix ARM quadword VDUP (core register). 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2009-03-17 12:19:58 +00:00
parent d78f399542
commit cbbccffc7a
1 changed files with 6 additions and 4 deletions
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10
target-arm/translate.c
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@ -2783,10 +2783,12 @@ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
} else if (size == 1) { } else if (size == 1) {
gen_neon_dup_low16(tmp); gen_neon_dup_low16(tmp);
} }
tmp2 = new_tmp(); for (n = 0; n <= pass * 2; n++) {
tcg_gen_mov_i32(tmp2, tmp); tmp2 = new_tmp();
neon_store_reg(rn, 0, tmp2); tcg_gen_mov_i32(tmp2, tmp);
neon_store_reg(rn, 1, tmp); neon_store_reg(rn, n, tmp2);
}
neon_store_reg(rn, n, tmp);
} else { } else {
/* VMOV */ /* VMOV */
switch (size) { switch (size) {