hw/arm/smmuv3: IOTLB emulation
We emulate a TLB cache of size SMMU_IOTLB_MAX_SIZE=256. It is implemented as a hash table whose key is a combination of the 16b asid and 48b IOVA (Jenkins hash). Entries are invalidated on TLB invalidation commands, either globally, or per asid, or per asid/iova. Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1529653501-15358-4-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Eric Auger
Peter Maydell
parent
32cfd7f39e
commit
cc27ed81cf
@ -24,11 +24,43 @@
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#include "qom/cpu.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "qemu/jhash.h"
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#include "qemu/error-report.h"
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#include "hw/arm/smmu-common.h"
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#include "smmu-internal.h"
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/* IOTLB Management */
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inline void smmu_iotlb_inv_all(SMMUState *s)
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{
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trace_smmu_iotlb_inv_all();
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g_hash_table_remove_all(s->iotlb);
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}
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static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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gpointer user_data)
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{
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uint16_t asid = *(uint16_t *)user_data;
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SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
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return iotlb_key->asid == asid;
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}
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inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova)
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{
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SMMUIOTLBKey key = {.asid = asid, .iova = iova};
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trace_smmu_iotlb_inv_iova(asid, iova);
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g_hash_table_remove(s->iotlb, &key);
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}
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inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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{
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trace_smmu_iotlb_inv_asid(asid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
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}
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/* VMSAv8-64 Translation */
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/**
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@ -328,6 +360,31 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid)
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return NULL;
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}
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static guint smmu_iotlb_key_hash(gconstpointer v)
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{
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SMMUIOTLBKey *key = (SMMUIOTLBKey *)v;
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uint32_t a, b, c;
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/* Jenkins hash */
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a = b = c = JHASH_INITVAL + sizeof(*key);
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a += key->asid;
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b += extract64(key->iova, 0, 32);
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c += extract64(key->iova, 32, 32);
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__jhash_mix(a, b, c);
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__jhash_final(a, b, c);
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return c;
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}
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static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
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{
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const SMMUIOTLBKey *k1 = v1;
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const SMMUIOTLBKey *k2 = v2;
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return (k1->asid == k2->asid) && (k1->iova == k2->iova);
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}
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static void smmu_base_realize(DeviceState *dev, Error **errp)
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{
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SMMUState *s = ARM_SMMU(dev);
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@ -340,6 +397,8 @@ static void smmu_base_realize(DeviceState *dev, Error **errp)
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return;
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}
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s->configs = g_hash_table_new_full(NULL, NULL, NULL, g_free);
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s->iotlb = g_hash_table_new_full(smmu_iotlb_key_hash, smmu_iotlb_key_equal,
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g_free, g_free);
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s->smmu_pcibus_by_busptr = g_hash_table_new(NULL, NULL);
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if (s->primary_bus) {
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@ -354,6 +413,7 @@ static void smmu_base_reset(DeviceState *dev)
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SMMUState *s = ARM_SMMU(dev);
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g_hash_table_remove_all(s->configs);
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g_hash_table_remove_all(s->iotlb);
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}
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static Property smmu_dev_properties[] = {
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@ -605,6 +605,10 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid};
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SMMUPTWEventInfo ptw_info = {};
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SMMUTranslationStatus status;
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SMMUState *bs = ARM_SMMU(s);
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uint64_t page_mask, aligned_addr;
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IOMMUTLBEntry *cached_entry = NULL;
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SMMUTransTableInfo *tt;
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SMMUTransCfg *cfg = NULL;
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IOMMUTLBEntry entry = {
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.target_as = &address_space_memory,
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@ -613,6 +617,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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SMMUIOTLBKey key, *new_key;
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qemu_mutex_lock(&s->mutex);
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@ -637,7 +642,57 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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goto epilogue;
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}
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if (smmu_ptw(cfg, addr, flag, &entry, &ptw_info)) {
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tt = select_tt(cfg, addr);
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if (!tt) {
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_TRANSLATION;
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event.u.f_translation.addr = addr;
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event.u.f_translation.rnw = flag & 0x1;
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}
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status = SMMU_TRANS_ERROR;
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goto epilogue;
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}
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page_mask = (1ULL << (tt->granule_sz)) - 1;
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aligned_addr = addr & ~page_mask;
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key.asid = cfg->asid;
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key.iova = aligned_addr;
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cached_entry = g_hash_table_lookup(bs->iotlb, &key);
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if (cached_entry) {
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cfg->iotlb_hits++;
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trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr,
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cfg->iotlb_hits, cfg->iotlb_misses,
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100 * cfg->iotlb_hits /
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(cfg->iotlb_hits + cfg->iotlb_misses));
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if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) {
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status = SMMU_TRANS_ERROR;
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if (event.record_trans_faults) {
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event.type = SMMU_EVT_F_PERMISSION;
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event.u.f_permission.addr = addr;
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event.u.f_permission.rnw = flag & 0x1;
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}
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} else {
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status = SMMU_TRANS_SUCCESS;
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}
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goto epilogue;
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}
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cfg->iotlb_misses++;
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trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask,
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cfg->iotlb_hits, cfg->iotlb_misses,
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100 * cfg->iotlb_hits /
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(cfg->iotlb_hits + cfg->iotlb_misses));
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if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {
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smmu_iotlb_inv_all(bs);
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}
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cached_entry = g_new0(IOMMUTLBEntry, 1);
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if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
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g_free(cached_entry);
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switch (ptw_info.type) {
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case SMMU_PTW_ERR_WALK_EABT:
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event.type = SMMU_EVT_F_WALK_EABT;
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@ -679,6 +734,10 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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}
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status = SMMU_TRANS_ERROR;
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} else {
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new_key = g_new0(SMMUIOTLBKey, 1);
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new_key->asid = cfg->asid;
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new_key->iova = aligned_addr;
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g_hash_table_insert(bs->iotlb, new_key, cached_entry);
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status = SMMU_TRANS_SUCCESS;
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}
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@ -687,6 +746,9 @@ epilogue:
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switch (status) {
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case SMMU_TRANS_SUCCESS:
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entry.perm = flag;
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entry.translated_addr = cached_entry->translated_addr +
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(addr & page_mask);
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entry.addr_mask = cached_entry->addr_mask;
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trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr,
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entry.translated_addr, entry.perm);
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break;
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@ -832,10 +894,39 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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smmuv3_flush_config(sdev);
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break;
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}
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case SMMU_CMD_TLBI_NH_ALL:
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case SMMU_CMD_TLBI_NH_ASID:
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case SMMU_CMD_TLBI_NH_VA:
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{
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uint16_t asid = CMD_ASID(&cmd);
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trace_smmuv3_cmdq_tlbi_nh_asid(asid);
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smmu_iotlb_inv_asid(bs, asid);
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break;
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}
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case SMMU_CMD_TLBI_NH_ALL:
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case SMMU_CMD_TLBI_NSNH_ALL:
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trace_smmuv3_cmdq_tlbi_nh();
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smmu_iotlb_inv_all(bs);
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break;
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case SMMU_CMD_TLBI_NH_VAA:
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{
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dma_addr_t addr = CMD_ADDR(&cmd);
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uint16_t vmid = CMD_VMID(&cmd);
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trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr);
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smmu_iotlb_inv_all(bs);
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break;
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}
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case SMMU_CMD_TLBI_NH_VA:
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{
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uint16_t asid = CMD_ASID(&cmd);
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uint16_t vmid = CMD_VMID(&cmd);
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dma_addr_t addr = CMD_ADDR(&cmd);
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bool leaf = CMD_LEAF(&cmd);
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trace_smmuv3_cmdq_tlbi_nh_va(vmid, asid, addr, leaf);
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smmu_iotlb_inv_iova(bs, asid, addr);
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break;
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}
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case SMMU_CMD_TLBI_EL3_ALL:
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case SMMU_CMD_TLBI_EL3_VA:
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case SMMU_CMD_TLBI_EL2_ALL:
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@ -844,7 +935,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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case SMMU_CMD_TLBI_EL2_VAA:
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case SMMU_CMD_TLBI_S12_VMALL:
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case SMMU_CMD_TLBI_S2_IPA:
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case SMMU_CMD_TLBI_NSNH_ALL:
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case SMMU_CMD_ATC_INV:
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case SMMU_CMD_PRI_RESP:
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case SMMU_CMD_RESUME:
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@ -12,6 +12,11 @@ smmu_ptw_invalid_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr,
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smmu_ptw_page_pte(int stage, int level, uint64_t iova, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t address) "stage=%d level=%d iova=0x%"PRIx64" base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" page address = 0x%"PRIx64
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smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, uint64_t pte, uint64_t iova, uint64_t gpa, int bsize_mb) "stage=%d level=%d base@=0x%"PRIx64" pte@=0x%"PRIx64" pte=0x%"PRIx64" iova=0x%"PRIx64" block address = 0x%"PRIx64" block size = %d MiB"
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smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
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smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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smmu_iotlb_inv_all(void) "IOTLB invalidate all"
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smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
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smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
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#hw/arm/smmuv3.c
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smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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@ -45,4 +50,8 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
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smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"
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smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
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@ -67,6 +67,8 @@ typedef struct SMMUTransCfg {
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uint8_t tbi; /* Top Byte Ignore */
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uint16_t asid;
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SMMUTransTableInfo tt[2];
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uint32_t iotlb_hits; /* counts IOTLB hits for this asid */
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uint32_t iotlb_misses; /* counts IOTLB misses for this asid */
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} SMMUTransCfg;
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typedef struct SMMUDevice {
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@ -89,6 +91,11 @@ typedef struct SMMUPciBus {
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SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */
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} SMMUPciBus;
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typedef struct SMMUIOTLBKey {
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uint64_t iova;
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uint16_t asid;
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} SMMUIOTLBKey;
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typedef struct SMMUState {
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/* <private> */
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SysBusDevice dev;
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@ -147,4 +154,10 @@ SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova);
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/* Return the iommu mr associated to @sid, or NULL if none */
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IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
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#define SMMU_IOTLB_MAX_SIZE 256
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void smmu_iotlb_inv_all(SMMUState *s);
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void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);
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#endif /* HW_ARM_SMMU_COMMON */
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