target/arm: Implement SVE floating-point arithmetic with immediate
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
abfdefd5bd
commit
cc48affe83
@ -809,6 +809,62 @@ DEF_HELPER_FLAGS_6(sve_fmulx_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_6(sve_fmulx_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadds_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadds_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fadds_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubs_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubs_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubs_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmuls_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmuls_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmuls_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubrs_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubrs_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fsubrs_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnms_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnms_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxnms_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnms_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnms_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fminnms_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxs_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxs_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmaxs_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmins_h, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmins_s, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_6(sve_fmins_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, i64, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_scvt_hh, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_scvt_sh, TCG_CALL_NO_RWG,
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@ -160,6 +160,10 @@
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@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
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&rpri_esz rn=%reg_movprfx
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# Two register operand, one one-bit floating-point operand.
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@rdn_i1 ........ esz:2 ......... pg:3 .... imm:1 rd:5 \
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&rpri_esz rn=%reg_movprfx
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# Two register operand, one encoded bitmask.
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@rdn_dbm ........ .. .... dbm:13 rd:5 \
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&rr_dbm rn=%reg_movprfx
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@ -744,6 +748,16 @@ FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
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FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
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FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
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# SVE floating-point arithmetic with immediate (predicated)
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FADD_zpzi 01100101 .. 011 000 100 ... 0000 . ..... @rdn_i1
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FSUB_zpzi 01100101 .. 011 001 100 ... 0000 . ..... @rdn_i1
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FMUL_zpzi 01100101 .. 011 010 100 ... 0000 . ..... @rdn_i1
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FSUBR_zpzi 01100101 .. 011 011 100 ... 0000 . ..... @rdn_i1
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FMAXNM_zpzi 01100101 .. 011 100 100 ... 0000 . ..... @rdn_i1
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FMINNM_zpzi 01100101 .. 011 101 100 ... 0000 . ..... @rdn_i1
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FMAX_zpzi 01100101 .. 011 110 100 ... 0000 . ..... @rdn_i1
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FMIN_zpzi 01100101 .. 011 111 100 ... 0000 . ..... @rdn_i1
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### SVE FP Multiply-Add Group
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# SVE floating-point multiply-accumulate writing addend
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@ -2997,6 +2997,75 @@ DO_ZPZZ_FP(sve_fmulx_d, uint64_t, , helper_vfp_mulxd)
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#undef DO_ZPZZ_FP
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/* Three-operand expander, with one scalar operand, controlled by
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* a predicate, with the extra float_status parameter.
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*/
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#define DO_ZPZS_FP(NAME, TYPE, H, OP) \
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void HELPER(NAME)(void *vd, void *vn, void *vg, uint64_t scalar, \
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void *status, uint32_t desc) \
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{ \
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intptr_t i = simd_oprsz(desc); \
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uint64_t *g = vg; \
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TYPE mm = scalar; \
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do { \
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uint64_t pg = g[(i - 1) >> 6]; \
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do { \
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i -= sizeof(TYPE); \
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if (likely((pg >> (i & 63)) & 1)) { \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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*(TYPE *)(vd + H(i)) = OP(nn, mm, status); \
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} \
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} while (i & 63); \
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} while (i != 0); \
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}
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DO_ZPZS_FP(sve_fadds_h, float16, H1_2, float16_add)
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DO_ZPZS_FP(sve_fadds_s, float32, H1_4, float32_add)
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DO_ZPZS_FP(sve_fadds_d, float64, , float64_add)
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DO_ZPZS_FP(sve_fsubs_h, float16, H1_2, float16_sub)
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DO_ZPZS_FP(sve_fsubs_s, float32, H1_4, float32_sub)
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DO_ZPZS_FP(sve_fsubs_d, float64, , float64_sub)
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DO_ZPZS_FP(sve_fmuls_h, float16, H1_2, float16_mul)
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DO_ZPZS_FP(sve_fmuls_s, float32, H1_4, float32_mul)
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DO_ZPZS_FP(sve_fmuls_d, float64, , float64_mul)
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static inline float16 subr_h(float16 a, float16 b, float_status *s)
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{
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return float16_sub(b, a, s);
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}
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static inline float32 subr_s(float32 a, float32 b, float_status *s)
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{
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return float32_sub(b, a, s);
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}
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static inline float64 subr_d(float64 a, float64 b, float_status *s)
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{
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return float64_sub(b, a, s);
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}
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DO_ZPZS_FP(sve_fsubrs_h, float16, H1_2, subr_h)
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DO_ZPZS_FP(sve_fsubrs_s, float32, H1_4, subr_s)
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DO_ZPZS_FP(sve_fsubrs_d, float64, , subr_d)
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DO_ZPZS_FP(sve_fmaxnms_h, float16, H1_2, float16_maxnum)
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DO_ZPZS_FP(sve_fmaxnms_s, float32, H1_4, float32_maxnum)
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DO_ZPZS_FP(sve_fmaxnms_d, float64, , float64_maxnum)
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DO_ZPZS_FP(sve_fminnms_h, float16, H1_2, float16_minnum)
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DO_ZPZS_FP(sve_fminnms_s, float32, H1_4, float32_minnum)
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DO_ZPZS_FP(sve_fminnms_d, float64, , float64_minnum)
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DO_ZPZS_FP(sve_fmaxs_h, float16, H1_2, float16_max)
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DO_ZPZS_FP(sve_fmaxs_s, float32, H1_4, float32_max)
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DO_ZPZS_FP(sve_fmaxs_d, float64, , float64_max)
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DO_ZPZS_FP(sve_fmins_h, float16, H1_2, float16_min)
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DO_ZPZS_FP(sve_fmins_s, float32, H1_4, float32_min)
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DO_ZPZS_FP(sve_fmins_d, float64, , float64_min)
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/* Fully general two-operand expander, controlled by a predicate,
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* With the extra float_status parameter.
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*/
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@ -32,6 +32,7 @@
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#include "exec/log.h"
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#include "trace-tcg.h"
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#include "translate-a64.h"
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#include "fpu/softfloat.h"
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typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t,
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@ -3533,6 +3534,80 @@ DO_FP3(FMULX, fmulx)
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#undef DO_FP3
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typedef void gen_helper_sve_fp2scalar(TCGv_ptr, TCGv_ptr, TCGv_ptr,
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TCGv_i64, TCGv_ptr, TCGv_i32);
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static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
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TCGv_i64 scalar, gen_helper_sve_fp2scalar *fn)
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{
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr t_zd, t_zn, t_pg, status;
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TCGv_i32 desc;
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t_zd = tcg_temp_new_ptr();
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t_zn = tcg_temp_new_ptr();
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t_pg = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, zd));
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tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, zn));
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tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg));
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status = get_fpstatus_ptr(is_fp16);
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desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
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fn(t_zd, t_zn, t_pg, scalar, status, desc);
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tcg_temp_free_i32(desc);
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tcg_temp_free_ptr(status);
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tcg_temp_free_ptr(t_pg);
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tcg_temp_free_ptr(t_zn);
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tcg_temp_free_ptr(t_zd);
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}
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static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm,
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gen_helper_sve_fp2scalar *fn)
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{
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TCGv_i64 temp = tcg_const_i64(imm);
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do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz == MO_16, temp, fn);
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tcg_temp_free_i64(temp);
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}
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#define DO_FP_IMM(NAME, name, const0, const1) \
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static bool trans_##NAME##_zpzi(DisasContext *s, arg_rpri_esz *a, \
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uint32_t insn) \
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{ \
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static gen_helper_sve_fp2scalar * const fns[3] = { \
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gen_helper_sve_##name##_h, \
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gen_helper_sve_##name##_s, \
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gen_helper_sve_##name##_d \
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}; \
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static uint64_t const val[3][2] = { \
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{ float16_##const0, float16_##const1 }, \
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{ float32_##const0, float32_##const1 }, \
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{ float64_##const0, float64_##const1 }, \
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}; \
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if (a->esz == 0) { \
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return false; \
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} \
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if (sve_access_check(s)) { \
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do_fp_imm(s, a, val[a->esz - 1][a->imm], fns[a->esz - 1]); \
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} \
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return true; \
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}
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#define float16_two make_float16(0x4000)
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#define float32_two make_float32(0x40000000)
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#define float64_two make_float64(0x4000000000000000ULL)
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DO_FP_IMM(FADD, fadds, half, one)
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DO_FP_IMM(FSUB, fsubs, half, one)
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DO_FP_IMM(FMUL, fmuls, half, two)
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DO_FP_IMM(FSUBR, fsubrs, half, one)
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DO_FP_IMM(FMAXNM, fmaxnms, zero, one)
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DO_FP_IMM(FMINNM, fminnms, zero, one)
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DO_FP_IMM(FMAX, fmaxs, zero, one)
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DO_FP_IMM(FMIN, fmins, zero, one)
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#undef DO_FP_IMM
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static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,
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gen_helper_gvec_4_ptr *fn)
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{
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