target/arm: Implement HSTR.TTEE
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses to the Thumb2EE TEECR and TEEHBR registers to be trapped to the hypervisor. Implement these traps. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
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@ -1541,6 +1541,8 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
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#define SCR_ENSCXT (1U << 25)
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#define SCR_ATA (1U << 26)
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#define HSTR_TTEE (1 << 16)
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/* Return the current FPSCR value. */
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uint32_t vfp_get_fpscr(CPUARMState *env);
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void vfp_set_fpscr(CPUARMState *env, uint32_t val);
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@ -2446,20 +2446,34 @@ static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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env->teecr = value;
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}
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static CPAccessResult teecr_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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/*
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* HSTR.TTEE only exists in v7A, not v8A, but v8A doesn't have T2EE
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* at all, so we don't need to check whether we're v8A.
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*/
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if (arm_current_el(env) < 2 && !arm_is_secure_below_el3(env) &&
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(env->cp15.hstr_el2 & HSTR_TTEE)) {
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return CP_ACCESS_TRAP_EL2;
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}
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return CP_ACCESS_OK;
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}
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static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
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bool isread)
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{
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if (arm_current_el(env) == 0 && (env->teecr & 1)) {
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return CP_ACCESS_TRAP;
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}
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return CP_ACCESS_OK;
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return teecr_access(env, ri, isread);
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}
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static const ARMCPRegInfo t2ee_cp_reginfo[] = {
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{ .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
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.resetvalue = 0,
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.writefn = teecr_write },
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.writefn = teecr_write, .accessfn = teecr_access },
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{ .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
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.access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
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.accessfn = teehbr_access, .resetvalue = 0 },
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