target/arm: Mark LDFF1 and LDNF1 as non-streaming
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -59,7 +59,5 @@ FAIL 0001 1110 0111 1110 0000 00-- ---- ---- # FJCVTZS
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# --11 1100 --1- ---- ---- ---- ---- --10 # Load/store FP register (register offset)
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# --11 1101 ---- ---- ---- ---- ---- ---- # Load/store FP register (scaled imm)
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FAIL 1010 010- ---- ---- 011- ---- ---- ---- # SVE contiguous FF load (scalar+scalar)
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FAIL 1010 010- ---1 ---- 101- ---- ---- ---- # SVE contiguous NF load (scalar+imm)
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FAIL 1010 010- -01- ---- 000- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+scalar)
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FAIL 1010 010- -010 ---- 001- ---- ---- ---- # SVE load & replicate 32 bytes (scalar+imm)
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@ -4805,6 +4805,7 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rprr_load *a)
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if (!dc_isar_feature(aa64_sve, s)) {
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return false;
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}
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s->is_nonstreaming = true;
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if (sve_access_check(s)) {
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TCGv_i64 addr = new_tmp_a64(s);
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tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype));
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@ -4906,6 +4907,7 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpri_load *a)
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if (!dc_isar_feature(aa64_sve, s)) {
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return false;
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}
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s->is_nonstreaming = true;
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if (sve_access_check(s)) {
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int vsz = vec_full_reg_size(s);
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int elements = vsz >> dtype_esz[a->dtype];
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