hw/arm/smmuv3: Add CMDs related to stage-2
CMD_TLBI_S2_IPA: As S1+S2 is not enabled, for now this can be the same as CMD_TLBI_NH_VAA. CMD_TLBI_S12_VMALL: Added new function to invalidate TLB by VMID. For stage-1 only commands, add a check to throw CERROR_ILL if used when stage-1 is not supported. Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-9-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Mostafa Saleh
Peter Maydell
parent
2eaeb7d593
commit
ccc3ee3871
@ -135,6 +135,16 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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return SMMU_IOTLB_ASID(*iotlb_key) == asid;
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}
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static gboolean smmu_hash_remove_by_vmid(gpointer key, gpointer value,
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gpointer user_data)
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{
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uint16_t vmid = *(uint16_t *)user_data;
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SMMUIOTLBKey *iotlb_key = (SMMUIOTLBKey *)key;
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return SMMU_IOTLB_VMID(*iotlb_key) == vmid;
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}
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static gboolean smmu_hash_remove_by_asid_vmid_iova(gpointer key, gpointer value,
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gpointer user_data)
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{
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@ -187,6 +197,12 @@ void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid, &asid);
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}
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inline void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid)
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{
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trace_smmu_iotlb_inv_vmid(vmid);
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g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_vmid, &vmid);
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}
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/* VMSAv8-64 Translation */
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/**
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@ -1063,7 +1063,7 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,
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}
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}
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static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
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static void smmuv3_range_inval(SMMUState *s, Cmd *cmd)
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{
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dma_addr_t end, addr = CMD_ADDR(cmd);
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uint8_t type = CMD_TYPE(cmd);
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@ -1088,7 +1088,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
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}
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if (!tg) {
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trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
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trace_smmuv3_range_inval(vmid, asid, addr, tg, 1, ttl, leaf);
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smmuv3_inv_notifiers_iova(s, asid, addr, tg, 1);
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smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, 1, ttl);
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return;
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@ -1106,7 +1106,7 @@ static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)
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uint64_t mask = dma_aligned_pow2_mask(addr, end, 64);
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num_pages = (mask + 1) >> granule;
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trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
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trace_smmuv3_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);
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smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);
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smmu_iotlb_inv_iova(s, asid, vmid, addr, tg, num_pages, ttl);
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addr += mask + 1;
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@ -1240,12 +1240,22 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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{
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uint16_t asid = CMD_ASID(&cmd);
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if (!STAGE1_SUPPORTED(s)) {
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cmd_error = SMMU_CERROR_ILL;
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break;
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}
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trace_smmuv3_cmdq_tlbi_nh_asid(asid);
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smmu_inv_notifiers_all(&s->smmu_state);
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smmu_iotlb_inv_asid(bs, asid);
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break;
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}
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case SMMU_CMD_TLBI_NH_ALL:
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if (!STAGE1_SUPPORTED(s)) {
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cmd_error = SMMU_CERROR_ILL;
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break;
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}
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QEMU_FALLTHROUGH;
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case SMMU_CMD_TLBI_NSNH_ALL:
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trace_smmuv3_cmdq_tlbi_nh();
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smmu_inv_notifiers_all(&s->smmu_state);
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@ -1253,7 +1263,36 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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break;
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case SMMU_CMD_TLBI_NH_VAA:
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case SMMU_CMD_TLBI_NH_VA:
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smmuv3_s1_range_inval(bs, &cmd);
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if (!STAGE1_SUPPORTED(s)) {
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cmd_error = SMMU_CERROR_ILL;
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break;
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}
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smmuv3_range_inval(bs, &cmd);
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break;
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case SMMU_CMD_TLBI_S12_VMALL:
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{
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uint16_t vmid = CMD_VMID(&cmd);
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if (!STAGE2_SUPPORTED(s)) {
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cmd_error = SMMU_CERROR_ILL;
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break;
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}
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trace_smmuv3_cmdq_tlbi_s12_vmid(vmid);
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smmu_inv_notifiers_all(&s->smmu_state);
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smmu_iotlb_inv_vmid(bs, vmid);
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break;
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}
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case SMMU_CMD_TLBI_S2_IPA:
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if (!STAGE2_SUPPORTED(s)) {
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cmd_error = SMMU_CERROR_ILL;
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break;
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}
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/*
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* As currently only either s1 or s2 are supported
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* we can reuse same function for s2.
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*/
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smmuv3_range_inval(bs, &cmd);
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break;
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case SMMU_CMD_TLBI_EL3_ALL:
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case SMMU_CMD_TLBI_EL3_VA:
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@ -1261,8 +1300,6 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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case SMMU_CMD_TLBI_EL2_ASID:
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case SMMU_CMD_TLBI_EL2_VA:
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case SMMU_CMD_TLBI_EL2_VAA:
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case SMMU_CMD_TLBI_S12_VMALL:
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case SMMU_CMD_TLBI_S2_IPA:
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case SMMU_CMD_ATC_INV:
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case SMMU_CMD_PRI_RESP:
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case SMMU_CMD_RESUME:
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@ -1271,12 +1308,14 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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break;
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default:
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cmd_error = SMMU_CERROR_ILL;
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qemu_log_mask(LOG_GUEST_ERROR,
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"Illegal command type: %d\n", CMD_TYPE(&cmd));
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break;
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}
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qemu_mutex_unlock(&s->mutex);
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if (cmd_error) {
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if (cmd_error == SMMU_CERROR_ILL) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Illegal command type: %d\n", CMD_TYPE(&cmd));
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}
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break;
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}
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/*
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@ -12,6 +12,7 @@ smmu_ptw_block_pte(int stage, int level, uint64_t baseaddr, uint64_t pteaddr, ui
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smmu_get_pte(uint64_t baseaddr, int index, uint64_t pteaddr, uint64_t pte) "baseaddr=0x%"PRIx64" index=0x%x, pteaddr=0x%"PRIx64", pte=0x%"PRIx64
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smmu_iotlb_inv_all(void) "IOTLB invalidate all"
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smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
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smmu_iotlb_inv_vmid(uint16_t vmid) "IOTLB invalidate vmid=%d"
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smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
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smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
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smmu_iotlb_lookup_hit(uint16_t asid, uint16_t vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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@ -45,9 +46,10 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%x - end=0x%x"
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smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"
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smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"
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smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
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smmuv3_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"
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smmuv3_cmdq_tlbi_nh(void) ""
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smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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smmuv3_cmdq_tlbi_s12_vmid(uint16_t vmid) "vmid=%d"
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smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
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smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
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smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
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@ -193,6 +193,7 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint16_t vmid, uint64_t iova,
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uint8_t tg, uint8_t level);
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void smmu_iotlb_inv_all(SMMUState *s);
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void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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void smmu_iotlb_inv_vmid(SMMUState *s, uint16_t vmid);
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void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
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uint8_t tg, uint64_t num_pages, uint8_t ttl);
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