target/ppc: Introduce powerpc_excp_7xx
Introduce a new powerpc_excp function specific for PowerPC 7xx CPUs (740, 745, 750, 750cl, 750cx, 750fx, 750gx, 755). This commit copies powerpc_excp_legacy verbatim so the next one has a clean diff. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220204173430.1457358-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Fabiano Rosas
Cédric Le Goater
parent
fd7dc4bb78
commit
ccfca2fca5
@ -741,6 +741,472 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
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powerpc_set_excp_state(cpu, vector, new_msr);
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}
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static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
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{
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CPUState *cs = CPU(cpu);
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CPUPPCState *env = &cpu->env;
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int excp_model = env->excp_model;
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target_ulong msr, new_msr, vector;
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int srr0, srr1, lev = -1;
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if (excp <= POWERPC_EXCP_NONE || excp >= POWERPC_EXCP_NB) {
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cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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}
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qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
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" => %s (%d) error=%02x\n", env->nip, powerpc_excp_name(excp),
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excp, env->error_code);
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/* new srr1 value excluding must-be-zero bits */
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if (excp_model == POWERPC_EXCP_BOOKE) {
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msr = env->msr;
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} else {
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msr = env->msr & ~0x783f0000ULL;
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}
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/*
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* new interrupt handler msr preserves existing HV and ME unless
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* explicitly overriden
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*/
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new_msr = env->msr & (((target_ulong)1 << MSR_ME) | MSR_HVB);
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/* target registers */
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srr0 = SPR_SRR0;
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srr1 = SPR_SRR1;
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/*
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* check for special resume at 0x100 from doze/nap/sleep/winkle on
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* P7/P8/P9
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*/
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if (env->resume_as_sreset) {
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excp = powerpc_reset_wakeup(cs, env, excp, &msr);
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}
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/*
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* Hypervisor emulation assistance interrupt only exists on server
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* arch 2.05 server or later. We also don't want to generate it if
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* we don't have HVB in msr_mask (PAPR mode).
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*/
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if (excp == POWERPC_EXCP_HV_EMU
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#if defined(TARGET_PPC64)
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&& !(mmu_is_64bit(env->mmu_model) && (env->msr_mask & MSR_HVB))
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#endif /* defined(TARGET_PPC64) */
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) {
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excp = POWERPC_EXCP_PROGRAM;
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}
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#ifdef TARGET_PPC64
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/*
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* SPEU and VPU share the same IVOR but they exist in different
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* processors. SPEU is e500v1/2 only and VPU is e6500 only.
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*/
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if (excp_model == POWERPC_EXCP_BOOKE && excp == POWERPC_EXCP_VPU) {
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excp = POWERPC_EXCP_SPEU;
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}
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#endif
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vector = env->excp_vectors[excp];
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if (vector == (target_ulong)-1ULL) {
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cpu_abort(cs, "Raised an exception without defined vector %d\n",
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excp);
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}
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vector |= env->excp_prefix;
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switch (excp) {
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case POWERPC_EXCP_CRITICAL: /* Critical input */
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switch (excp_model) {
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case POWERPC_EXCP_40x:
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srr0 = SPR_40x_SRR2;
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srr1 = SPR_40x_SRR3;
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break;
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case POWERPC_EXCP_BOOKE:
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srr0 = SPR_BOOKE_CSRR0;
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srr1 = SPR_BOOKE_CSRR1;
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break;
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case POWERPC_EXCP_6xx:
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break;
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default:
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goto excp_invalid;
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}
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break;
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case POWERPC_EXCP_MCHECK: /* Machine check exception */
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if (msr_me == 0) {
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/*
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* Machine check exception is not enabled. Enter
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* checkstop state.
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*/
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fprintf(stderr, "Machine check while not allowed. "
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"Entering checkstop state\n");
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if (qemu_log_separate()) {
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qemu_log("Machine check while not allowed. "
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"Entering checkstop state\n");
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}
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cs->halted = 1;
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cpu_interrupt_exittb(cs);
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}
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if (env->msr_mask & MSR_HVB) {
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/*
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* ISA specifies HV, but can be delivered to guest with HV
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* clear (e.g., see FWNMI in PAPR).
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*/
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new_msr |= (target_ulong)MSR_HVB;
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}
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/* machine check exceptions don't have ME set */
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new_msr &= ~((target_ulong)1 << MSR_ME);
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/* XXX: should also have something loaded in DAR / DSISR */
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switch (excp_model) {
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case POWERPC_EXCP_40x:
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srr0 = SPR_40x_SRR2;
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srr1 = SPR_40x_SRR3;
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break;
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case POWERPC_EXCP_BOOKE:
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/* FIXME: choose one or the other based on CPU type */
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srr0 = SPR_BOOKE_MCSRR0;
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srr1 = SPR_BOOKE_MCSRR1;
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env->spr[SPR_BOOKE_CSRR0] = env->nip;
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env->spr[SPR_BOOKE_CSRR1] = msr;
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break;
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default:
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break;
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}
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break;
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case POWERPC_EXCP_DSI: /* Data storage exception */
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trace_ppc_excp_dsi(env->spr[SPR_DSISR], env->spr[SPR_DAR]);
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break;
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case POWERPC_EXCP_ISI: /* Instruction storage exception */
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trace_ppc_excp_isi(msr, env->nip);
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msr |= env->error_code;
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break;
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case POWERPC_EXCP_EXTERNAL: /* External input */
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{
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bool lpes0;
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cs = CPU(cpu);
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/*
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* Exception targeting modifiers
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*
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* LPES0 is supported on POWER7/8/9
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* LPES1 is not supported (old iSeries mode)
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*
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* On anything else, we behave as if LPES0 is 1
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* (externals don't alter MSR:HV)
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*/
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#if defined(TARGET_PPC64)
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if (excp_model == POWERPC_EXCP_POWER7 ||
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excp_model == POWERPC_EXCP_POWER8 ||
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excp_model == POWERPC_EXCP_POWER9 ||
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excp_model == POWERPC_EXCP_POWER10) {
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lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
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} else
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#endif /* defined(TARGET_PPC64) */
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{
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lpes0 = true;
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}
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if (!lpes0) {
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new_msr |= (target_ulong)MSR_HVB;
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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srr0 = SPR_HSRR0;
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srr1 = SPR_HSRR1;
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}
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if (env->mpic_proxy) {
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/* IACK the IRQ on delivery */
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env->spr[SPR_BOOKE_EPR] = ldl_phys(cs->as, env->mpic_iack);
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}
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break;
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}
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case POWERPC_EXCP_ALIGN: /* Alignment exception */
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/* Get rS/rD and rA from faulting opcode */
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/*
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* Note: the opcode fields will not be set properly for a
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* direct store load/store, but nobody cares as nobody
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* actually uses direct store segments.
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*/
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env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
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break;
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case POWERPC_EXCP_PROGRAM: /* Program exception */
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switch (env->error_code & ~0xF) {
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case POWERPC_EXCP_FP:
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if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
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trace_ppc_excp_fp_ignore();
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cs->exception_index = POWERPC_EXCP_NONE;
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env->error_code = 0;
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return;
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}
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/*
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* FP exceptions always have NIP pointing to the faulting
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* instruction, so always use store_next and claim we are
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* precise in the MSR.
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*/
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msr |= 0x00100000;
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env->spr[SPR_BOOKE_ESR] = ESR_FP;
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break;
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case POWERPC_EXCP_INVAL:
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trace_ppc_excp_inval(env->nip);
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msr |= 0x00080000;
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env->spr[SPR_BOOKE_ESR] = ESR_PIL;
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break;
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case POWERPC_EXCP_PRIV:
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msr |= 0x00040000;
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env->spr[SPR_BOOKE_ESR] = ESR_PPR;
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break;
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case POWERPC_EXCP_TRAP:
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msr |= 0x00020000;
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env->spr[SPR_BOOKE_ESR] = ESR_PTR;
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break;
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default:
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/* Should never occur */
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cpu_abort(cs, "Invalid program exception %d. Aborting\n",
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env->error_code);
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break;
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}
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break;
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case POWERPC_EXCP_SYSCALL: /* System call exception */
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lev = env->error_code;
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if ((lev == 1) && cpu->vhyp) {
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dump_hcall(env);
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} else {
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dump_syscall(env);
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}
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/*
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* We need to correct the NIP which in this case is supposed
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* to point to the next instruction
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*/
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env->nip += 4;
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/* "PAPR mode" built-in hypercall emulation */
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if ((lev == 1) && cpu->vhyp) {
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PPCVirtualHypervisorClass *vhc =
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PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
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vhc->hypercall(cpu->vhyp, cpu);
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return;
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}
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if (lev == 1) {
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new_msr |= (target_ulong)MSR_HVB;
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}
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break;
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case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */
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lev = env->error_code;
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dump_syscall(env);
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env->nip += 4;
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new_msr |= env->msr & ((target_ulong)1 << MSR_EE);
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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vector += lev * 0x20;
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env->lr = env->nip;
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env->ctr = msr;
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break;
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case POWERPC_EXCP_FPU: /* Floating-point unavailable exception */
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case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
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case POWERPC_EXCP_DECR: /* Decrementer exception */
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break;
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case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
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/* FIT on 4xx */
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trace_ppc_excp_print("FIT");
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break;
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case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
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trace_ppc_excp_print("WDT");
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switch (excp_model) {
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case POWERPC_EXCP_BOOKE:
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srr0 = SPR_BOOKE_CSRR0;
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srr1 = SPR_BOOKE_CSRR1;
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break;
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default:
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break;
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}
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break;
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case POWERPC_EXCP_DTLB: /* Data TLB error */
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case POWERPC_EXCP_ITLB: /* Instruction TLB error */
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break;
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case POWERPC_EXCP_DEBUG: /* Debug interrupt */
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if (env->flags & POWERPC_FLAG_DE) {
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/* FIXME: choose one or the other based on CPU type */
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srr0 = SPR_BOOKE_DSRR0;
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srr1 = SPR_BOOKE_DSRR1;
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env->spr[SPR_BOOKE_CSRR0] = env->nip;
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env->spr[SPR_BOOKE_CSRR1] = msr;
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/* DBSR already modified by caller */
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} else {
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cpu_abort(cs, "Debug exception triggered on unsupported model\n");
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}
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break;
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case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable/VPU */
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env->spr[SPR_BOOKE_ESR] = ESR_SPV;
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break;
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case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
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break;
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case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
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srr0 = SPR_BOOKE_CSRR0;
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srr1 = SPR_BOOKE_CSRR1;
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break;
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case POWERPC_EXCP_RESET: /* System reset exception */
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/* A power-saving exception sets ME, otherwise it is unchanged */
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if (msr_pow) {
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/* indicate that we resumed from power save mode */
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msr |= 0x10000;
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new_msr |= ((target_ulong)1 << MSR_ME);
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}
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if (env->msr_mask & MSR_HVB) {
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/*
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* ISA specifies HV, but can be delivered to guest with HV
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* clear (e.g., see FWNMI in PAPR, NMI injection in QEMU).
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*/
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new_msr |= (target_ulong)MSR_HVB;
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} else {
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if (msr_pow) {
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cpu_abort(cs, "Trying to deliver power-saving system reset "
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"exception %d with no HV support\n", excp);
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}
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}
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break;
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case POWERPC_EXCP_DSEG: /* Data segment exception */
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case POWERPC_EXCP_ISEG: /* Instruction segment exception */
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case POWERPC_EXCP_TRACE: /* Trace exception */
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break;
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case POWERPC_EXCP_HISI: /* Hypervisor instruction storage exception */
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msr |= env->error_code;
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/* fall through */
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case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
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case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
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case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
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case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment exception */
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case POWERPC_EXCP_SDOOR_HV: /* Hypervisor Doorbell interrupt */
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case POWERPC_EXCP_HV_EMU:
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case POWERPC_EXCP_HVIRT: /* Hypervisor virtualization */
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srr0 = SPR_HSRR0;
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srr1 = SPR_HSRR1;
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new_msr |= (target_ulong)MSR_HVB;
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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break;
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case POWERPC_EXCP_VPU: /* Vector unavailable exception */
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case POWERPC_EXCP_VSXU: /* VSX unavailable exception */
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case POWERPC_EXCP_FU: /* Facility unavailable exception */
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#ifdef TARGET_PPC64
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env->spr[SPR_FSCR] |= ((target_ulong)env->error_code << 56);
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#endif
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break;
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case POWERPC_EXCP_HV_FU: /* Hypervisor Facility Unavailable Exception */
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#ifdef TARGET_PPC64
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env->spr[SPR_HFSCR] |= ((target_ulong)env->error_code << FSCR_IC_POS);
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srr0 = SPR_HSRR0;
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srr1 = SPR_HSRR1;
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new_msr |= (target_ulong)MSR_HVB;
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new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
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#endif
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break;
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case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
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trace_ppc_excp_print("PIT");
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break;
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case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
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case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
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case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
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switch (excp_model) {
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case POWERPC_EXCP_6xx:
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/* Swap temporary saved registers with GPRs */
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if (!(new_msr & ((target_ulong)1 << MSR_TGPR))) {
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new_msr |= (target_ulong)1 << MSR_TGPR;
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hreg_swap_gpr_tgpr(env);
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}
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/* fall through */
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case POWERPC_EXCP_7xx:
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ppc_excp_debug_sw_tlb(env, excp);
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msr |= env->crf[0] << 28;
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msr |= env->error_code; /* key, D/I, S/L bits */
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/* Set way using a LRU mechanism */
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msr |= ((env->last_way + 1) & (env->nb_ways - 1)) << 17;
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break;
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default:
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cpu_abort(cs, "Invalid TLB miss exception\n");
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break;
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}
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break;
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case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
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case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
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case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
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case POWERPC_EXCP_FPA: /* Floating-point assist exception */
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case POWERPC_EXCP_DABR: /* Data address breakpoint */
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case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
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case POWERPC_EXCP_SMI: /* System management interrupt */
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case POWERPC_EXCP_THERM: /* Thermal interrupt */
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case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
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case POWERPC_EXCP_VPUA: /* Vector assist exception */
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case POWERPC_EXCP_SOFTP: /* Soft patch exception */
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case POWERPC_EXCP_MAINT: /* Maintenance exception */
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case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
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case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
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cpu_abort(cs, "%s exception not implemented\n",
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powerpc_excp_name(excp));
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break;
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default:
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excp_invalid:
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cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
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break;
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}
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/* Sanity check */
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if (!(env->msr_mask & MSR_HVB)) {
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if (new_msr & MSR_HVB) {
|
||||
cpu_abort(cs, "Trying to deliver HV exception (MSR) %d with "
|
||||
"no HV support\n", excp);
|
||||
}
|
||||
if (srr0 == SPR_HSRR0) {
|
||||
cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
|
||||
"no HV support\n", excp);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Sort out endianness of interrupt, this differs depending on the
|
||||
* CPU, the HV mode, etc...
|
||||
*/
|
||||
if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) {
|
||||
new_msr |= (target_ulong)1 << MSR_LE;
|
||||
}
|
||||
|
||||
#if defined(TARGET_PPC64)
|
||||
if (excp_model == POWERPC_EXCP_BOOKE) {
|
||||
if (env->spr[SPR_BOOKE_EPCR] & EPCR_ICM) {
|
||||
/* Cat.64-bit: EPCR.ICM is copied to MSR.CM */
|
||||
new_msr |= (target_ulong)1 << MSR_CM;
|
||||
} else {
|
||||
vector = (uint32_t)vector;
|
||||
}
|
||||
} else {
|
||||
if (!msr_isf && !mmu_is_64bit(env->mmu_model)) {
|
||||
vector = (uint32_t)vector;
|
||||
} else {
|
||||
new_msr |= (target_ulong)1 << MSR_SF;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if (excp != POWERPC_EXCP_SYSCALL_VECTORED) {
|
||||
/* Save PC */
|
||||
env->spr[srr0] = env->nip;
|
||||
|
||||
/* Save MSR */
|
||||
env->spr[srr1] = msr;
|
||||
}
|
||||
|
||||
/* This can update new_msr and vector if AIL applies */
|
||||
ppc_excp_apply_ail(cpu, excp_model, excp, msr, &new_msr, &vector);
|
||||
|
||||
powerpc_set_excp_state(cpu, vector, new_msr);
|
||||
}
|
||||
|
||||
static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
|
||||
{
|
||||
CPUState *cs = CPU(cpu);
|
||||
@ -1942,6 +2408,9 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
|
||||
case POWERPC_EXCP_6xx:
|
||||
powerpc_excp_6xx(cpu, excp);
|
||||
break;
|
||||
case POWERPC_EXCP_7xx:
|
||||
powerpc_excp_7xx(cpu, excp);
|
||||
break;
|
||||
case POWERPC_EXCP_74xx:
|
||||
powerpc_excp_74xx(cpu, excp);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user