hw/mips/bootloader: Handle buffers as opaque arrays
It is irrelevant to the API what the buffers to fill are made of. In particular, some MIPS ISA have 16-bit wide instructions. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-2-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé
parent
14c2b18414
commit
cd5066f861
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@ -55,16 +55,20 @@ static bool bootcpu_supports_isa(uint64_t isa_mask)
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}
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/* Base types */
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static void bl_gen_nop(uint32_t **p)
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static void bl_gen_nop(void **ptr)
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{
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stl_p(*p, 0);
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*p = *p + 1;
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uint32_t *p = *ptr;
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stl_p(p, 0);
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p++;
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*ptr = p;
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}
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static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
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static void bl_gen_r_type(void **ptr, uint8_t opcode,
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bl_reg rs, bl_reg rt, bl_reg rd,
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uint8_t shift, uint8_t funct)
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{
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uint32_t *p = *ptr;
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uint32_t insn = 0;
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insn = deposit32(insn, 26, 6, opcode);
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@ -74,13 +78,16 @@ static void bl_gen_r_type(uint32_t **p, uint8_t opcode,
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insn = deposit32(insn, 6, 5, shift);
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insn = deposit32(insn, 0, 6, funct);
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stl_p(*p, insn);
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*p = *p + 1;
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stl_p(p, insn);
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p++;
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*ptr = p;
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}
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static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
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static void bl_gen_i_type(void **ptr, uint8_t opcode,
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bl_reg rs, bl_reg rt, uint16_t imm)
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{
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uint32_t *p = *ptr;
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uint32_t insn = 0;
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insn = deposit32(insn, 26, 6, opcode);
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@ -88,12 +95,14 @@ static void bl_gen_i_type(uint32_t **p, uint8_t opcode,
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insn = deposit32(insn, 16, 5, rt);
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insn = deposit32(insn, 0, 16, imm);
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stl_p(*p, insn);
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*p = *p + 1;
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stl_p(p, insn);
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p++;
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*ptr = p;
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}
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/* Single instructions */
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static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
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static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
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{
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if (bootcpu_supports_isa(ISA_MIPS3)) {
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bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
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@ -102,28 +111,28 @@ static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa)
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}
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}
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static void bl_gen_jalr(uint32_t **p, bl_reg rs)
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static void bl_gen_jalr(void **p, bl_reg rs)
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{
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bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x09);
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}
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static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm)
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static void bl_gen_lui(void **p, bl_reg rt, uint16_t imm)
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{
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/* R6: It's a alias of AUI with RS = 0 */
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bl_gen_i_type(p, 0x0f, 0, rt, imm);
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}
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static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm)
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static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
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{
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bl_gen_i_type(p, 0x0d, rs, rt, imm);
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}
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static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
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static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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bl_gen_i_type(p, 0x2b, base, rt, offset);
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}
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static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
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static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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if (bootcpu_supports_isa(ISA_MIPS3)) {
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bl_gen_i_type(p, 0x3f, base, rt, offset);
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@ -133,13 +142,13 @@ static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset)
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}
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/* Pseudo instructions */
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static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm)
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static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
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{
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bl_gen_lui(p, rt, extract32(imm, 16, 16));
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bl_gen_ori(p, rt, rt, extract32(imm, 0, 16));
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}
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static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
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static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
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{
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bl_gen_li(p, rt, extract64(imm, 32, 32));
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bl_gen_dsll(p, rt, rt, 16);
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@ -148,7 +157,7 @@ static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm)
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bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
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}
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static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
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static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
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{
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if (bootcpu_supports_isa(ISA_MIPS3)) {
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bl_gen_dli(p, rt, imm); /* 64bit */
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@ -158,14 +167,14 @@ static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm)
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}
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/* Helpers */
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void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr)
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void bl_gen_jump_to(void **p, target_ulong jump_addr)
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{
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bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
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bl_gen_jalr(p, BL_REG_T9);
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bl_gen_nop(p); /* delay slot */
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}
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void bl_gen_jump_kernel(uint32_t **p,
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void bl_gen_jump_kernel(void **p,
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bool set_sp, target_ulong sp,
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bool set_a0, target_ulong a0,
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bool set_a1, target_ulong a1,
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@ -192,7 +201,7 @@ void bl_gen_jump_kernel(uint32_t **p,
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bl_gen_jump_to(p, kernel_addr);
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}
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void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
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void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
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{
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bl_gen_load_ulong(p, BL_REG_K0, val);
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bl_gen_load_ulong(p, BL_REG_K1, addr);
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@ -203,14 +212,14 @@ void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val)
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}
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}
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void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val)
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void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
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{
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bl_gen_li(p, BL_REG_K0, val);
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bl_gen_load_ulong(p, BL_REG_K1, addr);
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bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
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}
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void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val)
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void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
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{
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bl_gen_dli(p, BL_REG_K0, val);
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bl_gen_load_ulong(p, BL_REG_K1, addr);
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@ -323,7 +323,7 @@ static void boston_register_types(void)
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}
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type_init(boston_register_types)
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static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr)
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static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
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{
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uint64_t regaddr;
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@ -179,7 +179,7 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base,
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/* Second part of the bootloader */
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p = (uint32_t *)(base + 0x040);
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bl_gen_jump_kernel(&p,
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bl_gen_jump_kernel((void **)&p,
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true, ENVP_VADDR - 64,
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true, 2, true, ENVP_VADDR,
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true, ENVP_VADDR + 8,
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@ -844,6 +844,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
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uint64_t kernel_entry)
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{
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uint32_t *p;
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void *v;
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/* Small bootloader */
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p = (uint32_t *)base;
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@ -886,38 +887,39 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
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#else
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#define cpu_to_gt32 cpu_to_be32
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#endif
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v = p;
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/* move GT64120 registers from 0x14000000 to 0x1be00000 */
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bl_gen_write_u32(&p, /* GT_ISD */
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bl_gen_write_u32(&v, /* GT_ISD */
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cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
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cpu_to_gt32(0x1be00000 << 3));
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/* setup MEM-to-PCI0 mapping */
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/* setup PCI0 io window to 0x18000000-0x181fffff */
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bl_gen_write_u32(&p, /* GT_PCI0IOLD */
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bl_gen_write_u32(&v, /* GT_PCI0IOLD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
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cpu_to_gt32(0x18000000 << 3));
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bl_gen_write_u32(&p, /* GT_PCI0IOHD */
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bl_gen_write_u32(&v, /* GT_PCI0IOHD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
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cpu_to_gt32(0x08000000 << 3));
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/* setup PCI0 mem windows */
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bl_gen_write_u32(&p, /* GT_PCI0M0LD */
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bl_gen_write_u32(&v, /* GT_PCI0M0LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
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cpu_to_gt32(0x10000000 << 3));
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bl_gen_write_u32(&p, /* GT_PCI0M0HD */
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bl_gen_write_u32(&v, /* GT_PCI0M0HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
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cpu_to_gt32(0x07e00000 << 3));
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bl_gen_write_u32(&p, /* GT_PCI0M1LD */
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bl_gen_write_u32(&v, /* GT_PCI0M1LD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
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cpu_to_gt32(0x18200000 << 3));
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bl_gen_write_u32(&p, /* GT_PCI0M1HD */
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bl_gen_write_u32(&v, /* GT_PCI0M1HD */
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cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
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cpu_to_gt32(0x0bc00000 << 3));
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#undef cpu_to_gt32
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bl_gen_jump_kernel(&p,
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bl_gen_jump_kernel(&v,
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true, ENVP_VADDR - 64,
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/*
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* If semihosting is used, arguments have already been
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@ -928,6 +930,7 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr,
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true, ENVP_VADDR + 8,
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true, loaderparams.ram_low_size,
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kernel_entry);
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p = v;
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/* YAMON subroutines */
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p = (uint32_t *) (base + 0x800);
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@ -11,16 +11,16 @@
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#include "exec/cpu-defs.h"
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void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr);
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void bl_gen_jump_kernel(uint32_t **p,
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void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
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void bl_gen_jump_kernel(void **ptr,
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bool set_sp, target_ulong sp,
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bool set_a0, target_ulong a0,
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bool set_a1, target_ulong a1,
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bool set_a2, target_ulong a2,
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bool set_a3, target_ulong a3,
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target_ulong kernel_addr);
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void bl_gen_write_ulong(uint32_t **p, target_ulong addr, target_ulong val);
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void bl_gen_write_u32(uint32_t **p, target_ulong addr, uint32_t val);
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void bl_gen_write_u64(uint32_t **p, target_ulong addr, uint64_t val);
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void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
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void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
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void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
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#endif
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