target/i386: pass cr3 to mmu_translate

First step in unifying the nested and regular page table walk.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2021-02-26 11:31:56 -05:00
parent 661ff4879e
commit cd906d315d
1 changed files with 6 additions and 6 deletions

View File

@ -246,7 +246,7 @@ static hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
#define PG_ERROR_OK (-1)
static int mmu_translate(CPUState *cs, vaddr addr,
int is_write1, int mmu_idx,
uint64_t cr3, int is_write1, int mmu_idx,
vaddr *xlat, int *page_size, int *prot)
{
X86CPU *cpu = X86_CPU(cs);
@ -288,7 +288,7 @@ static int mmu_translate(CPUState *cs, vaddr addr,
}
if (la57) {
pml5e_addr = ((env->cr[3] & ~0xfff) +
pml5e_addr = ((cr3 & ~0xfff) +
(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
pml5e_addr = get_hphys(cs, pml5e_addr, MMU_DATA_STORE, NULL);
pml5e = x86_ldq_phys(cs, pml5e_addr);
@ -304,7 +304,7 @@ static int mmu_translate(CPUState *cs, vaddr addr,
}
ptep = pml5e ^ PG_NX_MASK;
} else {
pml5e = env->cr[3];
pml5e = cr3;
ptep = PG_NX_MASK | PG_USER_MASK | PG_RW_MASK;
}
@ -349,7 +349,7 @@ static int mmu_translate(CPUState *cs, vaddr addr,
#endif
{
/* XXX: load them when cr3 is loaded ? */
pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
pdpe_addr = ((cr3 & ~0x1f) + ((addr >> 27) & 0x18)) &
a20_mask;
pdpe_addr = get_hphys(cs, pdpe_addr, MMU_DATA_STORE, false);
pdpe = x86_ldq_phys(cs, pdpe_addr);
@ -403,7 +403,7 @@ static int mmu_translate(CPUState *cs, vaddr addr,
uint32_t pde;
/* page directory entry */
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) &
pde_addr = ((cr3 & ~0xfff) + ((addr >> 20) & 0xffc)) &
a20_mask;
pde_addr = get_hphys(cs, pde_addr, MMU_DATA_STORE, NULL);
pde = x86_ldl_phys(cs, pde_addr);
@ -573,7 +573,7 @@ static int handle_mmu_fault(CPUState *cs, vaddr addr, int size,
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
page_size = 4096;
} else {
error_code = mmu_translate(cs, addr, is_write1,
error_code = mmu_translate(cs, addr, env->cr[3], is_write1,
mmu_idx,
&paddr, &page_size, &prot);
}