hw/misc/tz-mpc.c: Implement registers
Implement the missing registers for the TZ MPC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-3-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
344f4b1581
commit
cdb6099818
140
hw/misc/tz-mpc.c
140
hw/misc/tz-mpc.c
@ -28,16 +28,23 @@ enum {
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/* Config registers */
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REG32(CTRL, 0x00)
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FIELD(CTRL, SEC_RESP, 4, 1)
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FIELD(CTRL, AUTOINC, 8, 1)
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FIELD(CTRL, LOCKDOWN, 31, 1)
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REG32(BLK_MAX, 0x10)
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REG32(BLK_CFG, 0x14)
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REG32(BLK_IDX, 0x18)
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REG32(BLK_LUT, 0x1c)
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REG32(INT_STAT, 0x20)
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FIELD(INT_STAT, IRQ, 0, 1)
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REG32(INT_CLEAR, 0x24)
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FIELD(INT_CLEAR, IRQ, 0, 1)
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REG32(INT_EN, 0x28)
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FIELD(INT_EN, IRQ, 0, 1)
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REG32(INT_INFO1, 0x2c)
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REG32(INT_INFO2, 0x30)
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REG32(INT_SET, 0x34)
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FIELD(INT_SET, IRQ, 0, 1)
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REG32(PIDR4, 0xfd0)
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REG32(PIDR5, 0xfd4)
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REG32(PIDR6, 0xfd8)
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@ -57,10 +64,25 @@ static const uint8_t tz_mpc_idregs[] = {
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0x0d, 0xf0, 0x05, 0xb1,
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};
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static void tz_mpc_irq_update(TZMPC *s)
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{
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qemu_set_irq(s->irq, s->int_stat && s->int_en);
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}
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static void tz_mpc_autoinc_idx(TZMPC *s, unsigned access_size)
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{
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/* Auto-increment BLK_IDX if necessary */
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if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) {
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s->blk_idx++;
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s->blk_idx %= s->blk_max;
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}
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}
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static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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@ -74,6 +96,38 @@ static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
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}
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switch (offset) {
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case A_CTRL:
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r = s->ctrl;
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break;
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case A_BLK_MAX:
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r = s->blk_max;
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break;
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case A_BLK_CFG:
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/* We are never in "init in progress state", so this just indicates
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* the block size. s->blocksize == (1 << BLK_CFG + 5), so
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* BLK_CFG == ctz32(s->blocksize) - 5
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*/
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r = ctz32(s->blocksize) - 5;
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break;
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case A_BLK_IDX:
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r = s->blk_idx;
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break;
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case A_BLK_LUT:
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r = s->blk_lut[s->blk_idx];
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tz_mpc_autoinc_idx(s, size);
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break;
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case A_INT_STAT:
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r = s->int_stat;
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break;
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case A_INT_EN:
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r = s->int_en;
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break;
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case A_INT_INFO1:
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r = s->int_info1;
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break;
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case A_INT_INFO2:
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r = s->int_info2;
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break;
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case A_PIDR4:
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case A_PIDR5:
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case A_PIDR6:
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@ -120,6 +174,7 @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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uint32_t offset = addr & ~0x3;
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trace_tz_mpc_reg_write(addr, value, size);
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@ -140,9 +195,15 @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
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uint32_t oldval;
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switch (offset) {
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/* As we add support for registers which need expansions
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* other than zeroes we'll fill in cases here.
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*/
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case A_CTRL:
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oldval = s->ctrl;
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break;
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case A_BLK_IDX:
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oldval = s->blk_idx;
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break;
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case A_BLK_LUT:
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oldval = s->blk_lut[s->blk_idx];
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break;
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default:
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oldval = 0;
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break;
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@ -150,7 +211,48 @@ static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
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value = deposit32(oldval, (addr & 3) * 8, size * 8, value);
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}
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if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) &&
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(offset == A_CTRL || offset == A_BLK_LUT || offset == A_INT_EN)) {
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/* Lockdown mode makes these three registers read-only, and
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* the only way out of it is to reset the device.
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*/
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qemu_log_mask(LOG_GUEST_ERROR, "TZ MPC register write to offset 0x%x "
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"while MPC is in lockdown mode\n", offset);
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return MEMTX_OK;
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}
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switch (offset) {
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case A_CTRL:
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/* We don't implement the 'data gating' feature so all other bits
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* are reserved and we make them RAZ/WI.
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*/
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s->ctrl = value & (R_CTRL_SEC_RESP_MASK |
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R_CTRL_AUTOINC_MASK |
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R_CTRL_LOCKDOWN_MASK);
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break;
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case A_BLK_IDX:
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s->blk_idx = value % s->blk_max;
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break;
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case A_BLK_LUT:
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s->blk_lut[s->blk_idx] = value;
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tz_mpc_autoinc_idx(s, size);
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break;
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case A_INT_CLEAR:
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if (value & R_INT_CLEAR_IRQ_MASK) {
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s->int_stat = 0;
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tz_mpc_irq_update(s);
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}
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break;
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case A_INT_EN:
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s->int_en = value & R_INT_EN_IRQ_MASK;
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tz_mpc_irq_update(s);
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break;
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case A_INT_SET:
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if (value & R_INT_SET_IRQ_MASK) {
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s->int_stat = R_INT_STAT_IRQ_MASK;
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tz_mpc_irq_update(s);
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}
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break;
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case A_PIDR4:
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case A_PIDR5:
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case A_PIDR6:
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@ -266,6 +368,16 @@ static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu)
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static void tz_mpc_reset(DeviceState *dev)
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{
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TZMPC *s = TZ_MPC(dev);
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s->ctrl = 0x00000100;
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s->blk_idx = 0;
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s->int_stat = 0;
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s->int_en = 1;
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s->int_info1 = 0;
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s->int_info2 = 0;
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memset(s->blk_lut, 0, s->blk_max * sizeof(uint32_t));
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}
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static void tz_mpc_init(Object *obj)
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@ -339,13 +451,35 @@ static void tz_mpc_realize(DeviceState *dev, Error **errp)
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"tz-mpc-downstream");
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address_space_init(&s->blocked_io_as, &s->blocked_io,
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"tz-mpc-blocked-io");
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s->blk_lut = g_new(uint32_t, s->blk_max);
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}
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static int tz_mpc_post_load(void *opaque, int version_id)
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{
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TZMPC *s = TZ_MPC(opaque);
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/* Check the incoming data doesn't point blk_idx off the end of blk_lut. */
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if (s->blk_idx >= s->blk_max) {
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return -1;
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}
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return 0;
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}
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static const VMStateDescription tz_mpc_vmstate = {
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.name = "tz-mpc",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = tz_mpc_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ctrl, TZMPC),
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VMSTATE_UINT32(blk_idx, TZMPC),
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VMSTATE_UINT32(int_stat, TZMPC),
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VMSTATE_UINT32(int_en, TZMPC),
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VMSTATE_UINT32(int_info1, TZMPC),
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VMSTATE_UINT32(int_info2, TZMPC),
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VMSTATE_VARRAY_UINT32(blk_lut, TZMPC, blk_max,
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0, vmstate_info_uint32, uint32_t),
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VMSTATE_END_OF_LIST()
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}
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};
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@ -48,6 +48,16 @@ struct TZMPC {
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/*< public >*/
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/* State */
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uint32_t ctrl;
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uint32_t blk_idx;
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uint32_t int_stat;
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uint32_t int_en;
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uint32_t int_info1;
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uint32_t int_info2;
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uint32_t *blk_lut;
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qemu_irq irq;
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/* Properties */
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