target/riscv: remove RISCV_FEATURE_DEBUG
RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20230222185205.355361-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -637,7 +637,7 @@ static void riscv_cpu_reset_hold(Object *obj)
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set_default_nan_mode(1, &env->fp_status);
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#ifndef CONFIG_USER_ONLY
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if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
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if (cpu->cfg.debug) {
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riscv_trigger_init(env);
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}
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@ -935,10 +935,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
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}
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}
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if (cpu->cfg.debug) {
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riscv_set_feature(env, RISCV_FEATURE_DEBUG);
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}
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#ifndef CONFIG_USER_ONLY
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if (cpu->cfg.ext_sstc) {
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@ -89,7 +89,6 @@ enum {
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RISCV_FEATURE_MMU,
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RISCV_FEATURE_PMP,
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RISCV_FEATURE_EPMP,
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RISCV_FEATURE_DEBUG
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};
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/* Privileged specification version */
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@ -105,7 +105,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TB_FLAGS, MSTATUS_HS_VS,
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get_field(env->mstatus_hs, MSTATUS_VS));
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}
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if (riscv_feature(env, RISCV_FEATURE_DEBUG) && !icount_enabled()) {
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if (cpu->cfg.debug && !icount_enabled()) {
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flags = FIELD_DP32(flags, TB_FLAGS, ITRIGGER, env->itrigger_enabled);
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}
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#endif
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@ -437,7 +437,7 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
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static RISCVException debug(CPURISCVState *env, int csrno)
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{
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if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
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if (riscv_cpu_cfg(env)->debug) {
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return RISCV_EXCP_NONE;
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}
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@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
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static bool debug_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_feature(env, RISCV_FEATURE_DEBUG);
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return cpu->cfg.debug;
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}
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static int debug_post_load(void *opaque, int version_id)
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