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target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT 

Implement VFP fp16 for VABS, VNEG and VSQRT. This is all
the fp16 insns that use the DO_VFP_2OP macro, because there
is no fp16 version of VMOV_reg.

Notes:
 * the gen_helper_vfp_negh already exists as we needed to create
   it for the fp16 multiply-add insns
 * as usual we need to use the f16 version of the fp_status;
   this is only relevant for VSQRT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-9-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-08-28 19:33:17 +01:00
parent 009a07335b
commit ce2d65a5d1
4 changed files with 55 additions and 0 deletions
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2
target/arm/helper.h
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@ -128,8 +128,10 @@ DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr)
DEF_HELPER_1(vfp_negh, f16, f16)
DEF_HELPER_1(vfp_negs, f32, f32)
DEF_HELPER_1(vfp_negd, f64, f64)
DEF_HELPER_1(vfp_absh, f16, f16)
DEF_HELPER_1(vfp_abss, f32, f32)
DEF_HELPER_1(vfp_absd, f64, f64)
DEF_HELPER_2(vfp_sqrth, f16, f16, env)
DEF_HELPER_2(vfp_sqrts, f32, f32, env)
DEF_HELPER_2(vfp_sqrtd, f64, f64, env)
DEF_HELPER_3(vfp_cmps, void, f32, f32, env)

40
target/arm/translate-vfp.c.inc
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@ -1469,6 +1469,38 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
return true;
}
static bool do_vfp_2op_hp(DisasContext *s, VFPGen2OpSPFn *fn, int vd, int vm)
{
/*
* Do a half-precision operation. Functionally this is
* the same as do_vfp_2op_sp(), except:
* - it doesn't need the VFP vector handling (fp16 is a
* v8 feature, and in v8 VFP vectors don't exist)
* - it does the aa32_fp16_arith feature test
*/
TCGv_i32 f0;
if (!dc_isar_feature(aa32_fp16_arith, s)) {
return false;
}
if (s->vec_len != 0 || s->vec_stride != 0) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
f0 = tcg_temp_new_i32();
neon_load_reg32(f0, vm);
fn(f0, f0);
neon_store_reg32(f0, vd);
tcg_temp_free_i32(f0);
return true;
}
static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
{
uint32_t delta_m = 0;
@ -2244,12 +2276,19 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
DO_VFP_2OP(VMOV_reg, sp, tcg_gen_mov_i32)
DO_VFP_2OP(VMOV_reg, dp, tcg_gen_mov_i64)
DO_VFP_2OP(VABS, hp, gen_helper_vfp_absh)
DO_VFP_2OP(VABS, sp, gen_helper_vfp_abss)
DO_VFP_2OP(VABS, dp, gen_helper_vfp_absd)
DO_VFP_2OP(VNEG, hp, gen_helper_vfp_negh)
DO_VFP_2OP(VNEG, sp, gen_helper_vfp_negs)
DO_VFP_2OP(VNEG, dp, gen_helper_vfp_negd)
static void gen_VSQRT_hp(TCGv_i32 vd, TCGv_i32 vm)
{
gen_helper_vfp_sqrth(vd, vm, cpu_env);
}
static void gen_VSQRT_sp(TCGv_i32 vd, TCGv_i32 vm)
{
gen_helper_vfp_sqrts(vd, vm, cpu_env);
@ -2260,6 +2299,7 @@ static void gen_VSQRT_dp(TCGv_i64 vd, TCGv_i64 vm)
gen_helper_vfp_sqrtd(vd, vm, cpu_env);
}
DO_VFP_2OP(VSQRT, hp, gen_VSQRT_hp)
DO_VFP_2OP(VSQRT, sp, gen_VSQRT_sp)
DO_VFP_2OP(VSQRT, dp, gen_VSQRT_dp)

3
target/arm/vfp.decode
View File

@ -162,12 +162,15 @@ VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \
VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss
VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd
VABS_hp ---- 1110 1.11 0000 .... 1001 11.0 .... @vfp_dm_ss
VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss
VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd
VNEG_hp ---- 1110 1.11 0001 .... 1001 01.0 .... @vfp_dm_ss
VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss
VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd
VSQRT_hp ---- 1110 1.11 0001 .... 1001 11.0 .... @vfp_dm_ss
VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss
VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd

10
target/arm/vfp_helper.c
View File

@ -276,6 +276,11 @@ float64 VFP_HELPER(neg, d)(float64 a)
return float64_chs(a);
}
dh_ctype_f16 VFP_HELPER(abs, h)(dh_ctype_f16 a)
{
return float16_abs(a);
}
float32 VFP_HELPER(abs, s)(float32 a)
{
return float32_abs(a);
@ -286,6 +291,11 @@ float64 VFP_HELPER(abs, d)(float64 a)
return float64_abs(a);
}
dh_ctype_f16 VFP_HELPER(sqrt, h)(dh_ctype_f16 a, CPUARMState *env)
{
return float16_sqrt(a, &env->vfp.fp_status_f16);
}
float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
{
return float32_sqrt(a, &env->vfp.fp_status);