target/s390x: Return exception from mmu_translate
Do not raise the exception directly within mmu_translate, but pass it back so that caller may do so. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20191001171614.8405-10-richard.henderson@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com>
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@ -140,8 +140,8 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_64)) {
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vaddr &= 0x7fffffff;
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vaddr &= 0x7fffffff;
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}
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}
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fail = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, true);
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excp = mmu_translate(env, vaddr, access_type, asc, &raddr, &prot, &tec);
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excp = 0; /* exception already raised */
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fail = excp;
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} else if (mmu_idx == MMU_REAL_IDX) {
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} else if (mmu_idx == MMU_REAL_IDX) {
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/* 31-Bit mode */
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_64)) {
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@ -52,6 +52,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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target_ulong raddr;
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target_ulong raddr;
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int prot;
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int prot;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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uint64_t tec;
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/* 31-Bit mode */
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/* 31-Bit mode */
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_64)) {
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@ -67,7 +68,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
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* We want to read code even if IEP is active. Use MMU_DATA_LOAD instead
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* We want to read code even if IEP is active. Use MMU_DATA_LOAD instead
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* of MMU_INST_FETCH.
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* of MMU_INST_FETCH.
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*/
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*/
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if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, false)) {
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if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, &tec)) {
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return -1;
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return -1;
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}
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}
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return raddr;
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return raddr;
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@ -360,7 +360,7 @@ void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
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/* mmu_helper.c */
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/* mmu_helper.c */
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, bool exc);
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target_ulong *raddr, int *flags, uint64_t *tec);
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int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
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int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
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target_ulong *addr, int *flags, uint64_t *tec);
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target_ulong *addr, int *flags, uint64_t *tec);
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@ -2364,8 +2364,8 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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uint32_t cc = 0;
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uint32_t cc = 0;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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uint64_t asc = env->psw.mask & PSW_MASK_ASC;
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uint64_t ret;
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uint64_t ret, tec;
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int old_exc, flags;
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int old_exc, flags, exc;
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/* XXX incomplete - has more corner cases */
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/* XXX incomplete - has more corner cases */
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if (!(env->psw.mask & PSW_MASK_64) && (addr >> 32)) {
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if (!(env->psw.mask & PSW_MASK_64) && (addr >> 32)) {
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@ -2373,7 +2373,14 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
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}
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}
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old_exc = cs->exception_index;
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old_exc = cs->exception_index;
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if (mmu_translate(env, addr, 0, asc, &ret, &flags, true)) {
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exc = mmu_translate(env, addr, 0, asc, &ret, &flags, &tec);
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if (exc) {
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/*
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* We don't care about ILEN or TEC, as we're not going to
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* deliver the exception -- thus resetting exception_index below.
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* TODO: clean this up.
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*/
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trigger_pgm_exception(env, exc, ILEN_UNWIND);
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cc = 3;
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cc = 3;
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}
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}
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if (cs->exception_index == EXCP_PGM) {
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if (cs->exception_index == EXCP_PGM) {
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@ -365,20 +365,18 @@ static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
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* @param raddr the translated address is stored to this pointer
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* @param raddr the translated address is stored to this pointer
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* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
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* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
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* @param exc true = inject a program check if a fault occurred
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* @param exc true = inject a program check if a fault occurred
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* @return 0 if the translation was successful, -1 if a fault occurred
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* @return 0 = success, != 0, the exception to raise
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*/
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*/
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, bool exc)
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target_ulong *raddr, int *flags, uint64_t *tec)
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{
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{
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/* Code accesses have an undefined ilc, let's use 2 bytes. */
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const int ilen = (rw == MMU_INST_FETCH) ? 2 : ILEN_AUTO;
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uint64_t tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
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(rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
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uint64_t asce;
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uint64_t asce;
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int r;
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int r;
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*tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
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(rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
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if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
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/*
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/*
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* If any part of this page is currently protected, make sure the
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* If any part of this page is currently protected, make sure the
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@ -390,12 +388,9 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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*/
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*/
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*flags |= PAGE_WRITE_INV;
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*flags |= PAGE_WRITE_INV;
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if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
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if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
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if (exc) {
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/* LAP sets bit 56 */
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/* LAP sets bit 56 */
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*tec |= 0x80;
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tec |= 0x80;
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return PGM_PROTECTION;
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trigger_access_exception(env, PGM_PROTECTION, ilen, tec);
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}
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return -EACCES;
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}
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}
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}
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}
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@ -425,30 +420,21 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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/* perform the DAT translation */
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/* perform the DAT translation */
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r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw);
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r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw);
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if (unlikely(r)) {
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if (unlikely(r)) {
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if (exc) {
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return r;
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trigger_access_exception(env, r, ilen, tec);
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}
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return -1;
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}
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}
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/* check for DAT protection */
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/* check for DAT protection */
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if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
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if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
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if (exc) {
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/* DAT sets bit 61 only */
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/* DAT sets bit 61 only */
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*tec |= 0x4;
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tec |= 0x4;
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return PGM_PROTECTION;
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trigger_access_exception(env, PGM_PROTECTION, ilen, tec);
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}
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return -1;
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}
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}
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/* check for Instruction-Execution-Protection */
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/* check for Instruction-Execution-Protection */
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if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
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if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
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if (exc) {
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/* IEP sets bit 56 and 61 */
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/* IEP sets bit 56 and 61 */
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*tec |= 0x84;
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tec |= 0x84;
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return PGM_PROTECTION;
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trigger_access_exception(env, PGM_PROTECTION, ilen, tec);
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}
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return -1;
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}
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}
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nodat:
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nodat:
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@ -472,9 +458,12 @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
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int ret, i, pflags;
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int ret, i, pflags;
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for (i = 0; i < nr_pages; i++) {
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for (i = 0; i < nr_pages; i++) {
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ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true);
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uint64_t tec;
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ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, &tec);
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if (ret) {
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if (ret) {
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return ret;
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trigger_access_exception(env, ret, ILEN_AUTO, tec);
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return -EFAULT;
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}
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}
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if (!address_space_access_valid(&address_space_memory, pages[i],
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if (!address_space_access_valid(&address_space_memory, pages[i],
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TARGET_PAGE_SIZE, is_write,
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TARGET_PAGE_SIZE, is_write,
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