stdvga: pass VGACommonState instead of PCIVGAState
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
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24cdff7c82
commit
cf45ec6a52
@ -76,16 +76,16 @@ static const VMStateDescription vmstate_vga_pci = {
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static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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uint64_t ret = 0;
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switch (size) {
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case 1:
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ret = vga_ioport_read(&d->vga, addr + 0x3c0);
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ret = vga_ioport_read(s, addr + 0x3c0);
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break;
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case 2:
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ret = vga_ioport_read(&d->vga, addr + 0x3c0);
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ret |= vga_ioport_read(&d->vga, addr + 0x3c1) << 8;
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ret = vga_ioport_read(s, addr + 0x3c0);
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ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
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break;
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}
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return ret;
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@ -94,11 +94,11 @@ static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
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static void pci_vga_ioport_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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switch (size) {
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case 1:
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vga_ioport_write(&d->vga, addr + 0x3c0, val);
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vga_ioport_write(s, addr + 0x3c0, val);
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break;
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case 2:
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/*
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@ -106,8 +106,8 @@ static void pci_vga_ioport_write(void *ptr, hwaddr addr,
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* indexed registers with a single word write because the
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* index byte is updated first.
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*/
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vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
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vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
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vga_ioport_write(s, addr + 0x3c0, val & 0xff);
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vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
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break;
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}
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}
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@ -125,21 +125,21 @@ static const MemoryRegionOps pci_vga_ioport_ops = {
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static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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return vbe_ioport_read_data(&d->vga, 0);
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vbe_ioport_write_index(s, 0, index);
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return vbe_ioport_read_data(s, 0);
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}
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static void pci_vga_bochs_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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vbe_ioport_write_data(&d->vga, 0, val);
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vbe_ioport_write_index(s, 0, index);
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vbe_ioport_write_data(s, 0, val);
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}
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static const MemoryRegionOps pci_vga_bochs_ops = {
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@ -154,13 +154,13 @@ static const MemoryRegionOps pci_vga_bochs_ops = {
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static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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switch (addr) {
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case PCI_VGA_QEXT_REG_SIZE:
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return PCI_VGA_QEXT_SIZE;
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case PCI_VGA_QEXT_REG_BYTEORDER:
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return d->vga.big_endian_fb ?
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return s->big_endian_fb ?
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PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
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default:
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return 0;
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@ -170,15 +170,15 @@ static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
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static void pci_vga_qext_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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VGACommonState *s = ptr;
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switch (addr) {
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case PCI_VGA_QEXT_REG_BYTEORDER:
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if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
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d->vga.big_endian_fb = true;
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s->big_endian_fb = true;
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}
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if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
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d->vga.big_endian_fb = false;
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s->big_endian_fb = false;
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}
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break;
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}
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@ -224,9 +224,9 @@ static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
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/* mmio bar for vga register access */
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if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
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memory_region_init(&d->mmio, NULL, "vga.mmio", 4096);
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memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, d,
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memory_region_init_io(&d->ioport, NULL, &pci_vga_ioport_ops, s,
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"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
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memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, d,
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memory_region_init_io(&d->bochs, NULL, &pci_vga_bochs_ops, s,
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"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
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memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
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@ -235,7 +235,7 @@ static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
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&d->bochs);
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if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
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memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, d,
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memory_region_init_io(&d->qext, NULL, &pci_vga_qext_ops, s,
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"qemu extended regs", PCI_VGA_QEXT_SIZE);
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memory_region_add_subregion(&d->mmio, PCI_VGA_QEXT_OFFSET,
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&d->qext);
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