From cf4ab1af296b8ef5d5a1dc65fda804b88ddd0553 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Mon, 17 Mar 2014 16:31:47 +0000 Subject: [PATCH] target-arm: A64: Fix bug in add_sub_ext handling of rn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit rn == 31 always means SP (not XZR) whether an add_sub_ext instruction is setting the flags or not; only rd has behaviour dependent on whether we are setting flags. Reported-by: Laurent Desnogues Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 1394822294-14837-3-git-send-email-peter.maydell@linaro.org --- target-arm/translate-a64.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 37252b7479..444dd8504d 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3096,12 +3096,11 @@ static void disas_add_sub_ext_reg(DisasContext *s, uint32_t insn) /* non-flag setting ops may use SP */ if (!setflags) { - tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rd = cpu_reg_sp(s, rd); } else { - tcg_rn = read_cpu_reg(s, rn, sf); tcg_rd = cpu_reg(s, rd); } + tcg_rn = read_cpu_reg_sp(s, rn, sf); tcg_rm = read_cpu_reg(s, rm, sf); ext_and_shift_reg(tcg_rm, tcg_rm, option, imm3);