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target-ppc: use the new TCG logical operations

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5503 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-10-21 11:29:55 +00:00
parent 1b581c440b
commit cf960816f9
1 changed files with 10 additions and 55 deletions
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65
target-ppc/translate.c
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@ -5730,7 +5730,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]); \
}
#define GEN_SPEOP_TCG_ARITH2(name) \
#define GEN_SPEOP_TCG_ARITH2(name, tcg_op) \
static always_inline void gen_##name (DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
@ -5741,7 +5741,7 @@ static always_inline void gen_##name (DisasContext *ctx) \
TCGv t1 = tcg_temp_new(TCG_TYPE_I64); \
gen_load_gpr64(t0, rA(ctx->opcode)); \
gen_load_gpr64(t1, rB(ctx->opcode)); \
gen_op_##name(t0, t1); \
tcg_op(t0, t0, t1); \
gen_store_gpr64(rD(ctx->opcode), t0); \
tcg_temp_free(t0); \
tcg_temp_free(t1); \
@ -5773,59 +5773,14 @@ static always_inline void gen_##name (DisasContext *ctx) \
}
/* Logical */
static always_inline void gen_op_evand (TCGv t0, TCGv t1)
{
tcg_gen_and_i64(t0, t0, t1);
}
static always_inline void gen_op_evandc (TCGv t0, TCGv t1)
{
tcg_gen_not_i64(t1, t1);
tcg_gen_and_i64(t0, t0, t1);
}
static always_inline void gen_op_evxor (TCGv t0, TCGv t1)
{
tcg_gen_xor_i64(t0, t0, t1);
}
static always_inline void gen_op_evor (TCGv t0, TCGv t1)
{
tcg_gen_or_i64(t0, t0, t1);
}
static always_inline void gen_op_evnor (TCGv t0, TCGv t1)
{
tcg_gen_or_i64(t0, t0, t1);
tcg_gen_not_i64(t0, t0);
}
static always_inline void gen_op_eveqv (TCGv t0, TCGv t1)
{
tcg_gen_xor_i64(t0, t0, t1);
tcg_gen_not_i64(t0, t0);
}
static always_inline void gen_op_evorc (TCGv t0, TCGv t1)
{
tcg_gen_not_i64(t1, t1);
tcg_gen_or_i64(t0, t0, t1);
}
static always_inline void gen_op_evnand (TCGv t0, TCGv t1)
{
tcg_gen_and_i64(t0, t0, t1);
tcg_gen_not_i64(t0, t0);
}
GEN_SPEOP_TCG_ARITH2(evand);
GEN_SPEOP_TCG_ARITH2(evandc);
GEN_SPEOP_TCG_ARITH2(evxor);
GEN_SPEOP_TCG_ARITH2(evor);
GEN_SPEOP_TCG_ARITH2(evnor);
GEN_SPEOP_TCG_ARITH2(eveqv);
GEN_SPEOP_TCG_ARITH2(evorc);
GEN_SPEOP_TCG_ARITH2(evnand);
GEN_SPEOP_TCG_ARITH2(evand, tcg_gen_and_i64);
GEN_SPEOP_TCG_ARITH2(evandc, tcg_gen_andc_i64);
GEN_SPEOP_TCG_ARITH2(evxor, tcg_gen_xor_i64);
GEN_SPEOP_TCG_ARITH2(evor, tcg_gen_or_i64);
GEN_SPEOP_TCG_ARITH2(evnor, tcg_gen_nor_i64);
GEN_SPEOP_TCG_ARITH2(eveqv, tcg_gen_eqv_i64);
GEN_SPEOP_TCG_ARITH2(evorc, tcg_gen_orc_i64);
GEN_SPEOP_TCG_ARITH2(evnand, tcg_gen_nand_i64);
GEN_SPEOP_ARITH2(evsrwu);
GEN_SPEOP_ARITH2(evsrws);
GEN_SPEOP_ARITH2(evslw);