hw/block: replace TABs with space
Bring the block files in line with the QEMU coding style, with spaces for indentation. This patch partially resolves the issue 371. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/371 Signed-off-by: Yeqi Fu <fufuyqqqqqq@gmail.com> Message-Id: <20230314095001.13801-1-fufuyqqqqqq@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
This commit is contained in:
Yeqi Fu
Thomas Huth
parent
0030b244a7
commit
d091b5b442
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@ -601,8 +601,8 @@ enum {
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};
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enum {
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FD_STATE_MULTI = 0x01, /* multi track flag */
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FD_STATE_FORMAT = 0x02, /* format flag */
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FD_STATE_MULTI = 0x01, /* multi track flag */
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FD_STATE_FORMAT = 0x02, /* format flag */
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};
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enum {
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208
hw/block/nand.c
208
hw/block/nand.c
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@ -30,33 +30,33 @@
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#include "qemu/module.h"
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#include "qom/object.h"
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_CMD_READ0 0x00
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# define NAND_CMD_READ1 0x01
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# define NAND_CMD_READ2 0x50
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# define NAND_CMD_LPREAD2 0x30
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# define NAND_CMD_NOSERIALREAD2 0x35
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# define NAND_CMD_RANDOMREAD1 0x05
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# define NAND_CMD_RANDOMREAD2 0xe0
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# define NAND_CMD_READID 0x90
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# define NAND_CMD_RESET 0xff
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# define NAND_CMD_PAGEPROGRAM1 0x80
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# define NAND_CMD_PAGEPROGRAM2 0x10
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# define NAND_CMD_CACHEPROGRAM2 0x15
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# define NAND_CMD_BLOCKERASE1 0x60
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# define NAND_CMD_BLOCKERASE2 0xd0
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# define NAND_CMD_READSTATUS 0x70
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# define NAND_CMD_COPYBACKPRG1 0x85
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_ERROR (1 << 0)
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# define NAND_IOSTATUS_PLANE0 (1 << 1)
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# define NAND_IOSTATUS_PLANE1 (1 << 2)
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# define NAND_IOSTATUS_PLANE2 (1 << 3)
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# define NAND_IOSTATUS_PLANE3 (1 << 4)
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# define NAND_IOSTATUS_READY (1 << 6)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define NAND_IOSTATUS_UNPROTCT (1 << 7)
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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# define MAX_PAGE 0x800
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# define MAX_OOB 0x40
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typedef struct NANDFlashState NANDFlashState;
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struct NANDFlashState {
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@ -102,40 +102,40 @@ static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
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}
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}
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_NO_AUTOINCR 0x00000001
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# define NAND_BUSWIDTH_16 0x00000002
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# define NAND_NO_PADDING 0x00000004
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# define NAND_CACHEPRG 0x00000008
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# define NAND_COPYBACK 0x00000010
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# define NAND_IS_AND 0x00000020
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# define NAND_4PAGE_ARRAY 0x00000040
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# define NAND_NO_READRDY 0x00000100
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# define NAND_SAMSUNG_LP (NAND_NO_PADDING | NAND_COPYBACK)
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# define NAND_IO
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (NAND_PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define PAGE(addr) ((addr) >> ADDR_SHIFT)
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# define PAGE_START(page) (PAGE(page) * (NAND_PAGE_SIZE + OOB_SIZE))
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# define PAGE_MASK ((1 << ADDR_SHIFT) - 1)
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# define OOB_SHIFT (PAGE_SHIFT - 5)
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# define OOB_SIZE (1 << OOB_SHIFT)
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# define SECTOR(addr) ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
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# define SECTOR_OFFSET(addr) ((addr) & ((511 >> PAGE_SHIFT) << 8))
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# define NAND_PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# define NAND_PAGE_SIZE 256
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# define PAGE_SHIFT 8
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define NAND_PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# define NAND_PAGE_SIZE 512
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# define PAGE_SHIFT 9
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# define PAGE_SECTORS 1
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# define ADDR_SHIFT 8
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# include "nand.c"
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# define NAND_PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# define NAND_PAGE_SIZE 2048
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# define PAGE_SHIFT 11
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# define PAGE_SECTORS 4
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# define ADDR_SHIFT 16
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# include "nand.c"
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/* Information based on Linux drivers/mtd/nand/raw/nand_ids.c */
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@ -148,79 +148,79 @@ static const struct {
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} nand_flash_ids[0x100] = {
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[0 ... 0xff] = { 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x6b] = { 4, 8, 9, 4, 0 },
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[0xe3] = { 4, 8, 9, 4, 0 },
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[0xe5] = { 4, 8, 9, 4, 0 },
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[0xd6] = { 8, 8, 9, 4, 0 },
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[0xe6] = { 8, 8, 9, 4, 0 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x33] = { 16, 8, 9, 5, 0 },
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[0x73] = { 16, 8, 9, 5, 0 },
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[0x43] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x53] = { 16, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x35] = { 32, 8, 9, 5, 0 },
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[0x75] = { 32, 8, 9, 5, 0 },
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[0x45] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x55] = { 32, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x36] = { 64, 8, 9, 5, 0 },
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[0x76] = { 64, 8, 9, 5, 0 },
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[0x46] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x56] = { 64, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x78] = { 128, 8, 9, 5, 0 },
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[0x39] = { 128, 8, 9, 5, 0 },
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[0x79] = { 128, 8, 9, 5, 0 },
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[0x72] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x49] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x74] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x59] = { 128, 16, 9, 5, NAND_BUSWIDTH_16 },
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[0x71] = { 256, 8, 9, 5, 0 },
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[0x71] = { 256, 8, 9, 5, 0 },
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/*
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* These are the new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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# define LP_OPTIONS (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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# define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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/* 512 Megabit */
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xa2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xf2] = { 64, 8, 0, 0, LP_OPTIONS },
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[0xb2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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[0xc2] = { 64, 16, 0, 0, LP_OPTIONS16 },
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/* 1 Gigabit */
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xa1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xf1] = { 128, 8, 0, 0, LP_OPTIONS },
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[0xb1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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[0xc1] = { 128, 16, 0, 0, LP_OPTIONS16 },
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/* 2 Gigabit */
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xaa] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xda] = { 256, 8, 0, 0, LP_OPTIONS },
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[0xba] = { 256, 16, 0, 0, LP_OPTIONS16 },
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[0xca] = { 256, 16, 0, 0, LP_OPTIONS16 },
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/* 4 Gigabit */
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xac] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xdc] = { 512, 8, 0, 0, LP_OPTIONS },
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[0xbc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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[0xcc] = { 512, 16, 0, 0, LP_OPTIONS16 },
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/* 8 Gigabit */
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xa3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xd3] = { 1024, 8, 0, 0, LP_OPTIONS },
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[0xb3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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[0xc3] = { 1024, 16, 0, 0, LP_OPTIONS16 },
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/* 16 Gigabit */
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xa5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xd5] = { 2048, 8, 0, 0, LP_OPTIONS },
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[0xb5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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[0xc5] = { 2048, 16, 0, 0, LP_OPTIONS16 },
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};
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static void nand_reset(DeviceState *dev)
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@ -812,4 +812,4 @@ static void glue(nand_init_, NAND_PAGE_SIZE)(NANDFlashState *s)
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# undef PAGE_SHIFT
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# undef PAGE_SECTORS
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# undef ADDR_SHIFT
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#endif /* NAND_IO */
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#endif /* NAND_IO */
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@ -35,10 +35,10 @@
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#include "qom/object.h"
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/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
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#define PAGE_SHIFT 11
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#define PAGE_SHIFT 11
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/* Fixed */
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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#define BLOCK_SHIFT (PAGE_SHIFT + 6)
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#define TYPE_ONE_NAND "onenand"
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OBJECT_DECLARE_SIMPLE_TYPE(OneNANDState, ONE_NAND)
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@ -408,23 +408,23 @@ static void onenand_command(OneNANDState *s)
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int b;
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int sec;
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void *buf;
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? \
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s->density_mask : 0)) << 6)) << (PAGE_SHIFT - 9));
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
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#define SETADDR(block, page) \
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sec = (s->addr[page] & 3) + \
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((((s->addr[page] >> 2) & 0x3f) + \
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(((s->addr[block] & 0xfff) | \
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(s->addr[block] >> 15 ? s->density_mask : 0)) \
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<< 6)) \
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<< (PAGE_SHIFT - 9));
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#define SETBUF_M() \
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buf = (s->bufaddr & 8) ? s->data[(s->bufaddr >> 2) & 1][0] : s->boot[0]; \
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buf += (s->bufaddr & 3) << 9;
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
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#define SETBUF_S() \
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buf = (s->bufaddr & 8) ? \
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s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
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buf += (s->bufaddr & 3) << 4;
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switch (s->command) {
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case 0x00: /* Load single/multiple sector data unit into buffer */
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case 0x00: /* Load single/multiple sector data unit into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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@ -443,7 +443,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x13: /* Load single/multiple spare sector into buffer */
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case 0x13: /* Load single/multiple spare sector into buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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@ -456,7 +456,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_LOAD;
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break;
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case 0x80: /* Program single/multiple sector data unit from buffer */
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case 0x80: /* Program single/multiple sector data unit from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_M()
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@ -475,7 +475,7 @@ static void onenand_command(OneNANDState *s)
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*/
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s->intstatus |= ONEN_INT | ONEN_INT_PROG;
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break;
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case 0x1a: /* Program single/multiple spare area sector from buffer */
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case 0x1a: /* Program single/multiple spare area sector from buffer */
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SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
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SETBUF_S()
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@ -488,7 +488,7 @@ static void onenand_command(OneNANDState *s)
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*/
|
||||
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
|
||||
break;
|
||||
case 0x1b: /* Copy-back program */
|
||||
case 0x1b: /* Copy-back program */
|
||||
SETBUF_S()
|
||||
|
||||
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
|
||||
|
|
@ -504,7 +504,7 @@ static void onenand_command(OneNANDState *s)
|
|||
s->intstatus |= ONEN_INT | ONEN_INT_PROG;
|
||||
break;
|
||||
|
||||
case 0x23: /* Unlock NAND array block(s) */
|
||||
case 0x23: /* Unlock NAND array block(s) */
|
||||
s->intstatus |= ONEN_INT;
|
||||
|
||||
/* XXX the previous (?) area should be locked automatically */
|
||||
|
|
@ -519,7 +519,7 @@ static void onenand_command(OneNANDState *s)
|
|||
s->wpstatus = s->blockwp[b] = ONEN_LOCK_UNLOCKED;
|
||||
}
|
||||
break;
|
||||
case 0x27: /* Unlock All NAND array blocks */
|
||||
case 0x27: /* Unlock All NAND array blocks */
|
||||
s->intstatus |= ONEN_INT;
|
||||
|
||||
for (b = 0; b < s->blocks; b ++) {
|
||||
|
|
@ -530,7 +530,7 @@ static void onenand_command(OneNANDState *s)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0x2a: /* Lock NAND array block(s) */
|
||||
case 0x2a: /* Lock NAND array block(s) */
|
||||
s->intstatus |= ONEN_INT;
|
||||
|
||||
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
|
||||
|
|
@ -544,7 +544,7 @@ static void onenand_command(OneNANDState *s)
|
|||
s->wpstatus = s->blockwp[b] = ONEN_LOCK_LOCKED;
|
||||
}
|
||||
break;
|
||||
case 0x2c: /* Lock-tight NAND array block(s) */
|
||||
case 0x2c: /* Lock-tight NAND array block(s) */
|
||||
s->intstatus |= ONEN_INT;
|
||||
|
||||
for (b = s->unladdr[0]; b <= s->unladdr[1]; b ++) {
|
||||
|
|
@ -559,13 +559,13 @@ static void onenand_command(OneNANDState *s)
|
|||
}
|
||||
break;
|
||||
|
||||
case 0x71: /* Erase-Verify-Read */
|
||||
case 0x71: /* Erase-Verify-Read */
|
||||
s->intstatus |= ONEN_INT;
|
||||
break;
|
||||
case 0x95: /* Multi-block erase */
|
||||
case 0x95: /* Multi-block erase */
|
||||
qemu_irq_pulse(s->intr);
|
||||
/* Fall through. */
|
||||
case 0x94: /* Block erase */
|
||||
case 0x94: /* Block erase */
|
||||
sec = ((s->addr[ONEN_BUF_BLOCK] & 0xfff) |
|
||||
(s->addr[ONEN_BUF_BLOCK] >> 15 ? s->density_mask : 0))
|
||||
<< (BLOCK_SHIFT - 9);
|
||||
|
|
@ -574,20 +574,20 @@ static void onenand_command(OneNANDState *s)
|
|||
|
||||
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
||||
break;
|
||||
case 0xb0: /* Erase suspend */
|
||||
case 0xb0: /* Erase suspend */
|
||||
break;
|
||||
case 0x30: /* Erase resume */
|
||||
case 0x30: /* Erase resume */
|
||||
s->intstatus |= ONEN_INT | ONEN_INT_ERASE;
|
||||
break;
|
||||
|
||||
case 0xf0: /* Reset NAND Flash core */
|
||||
case 0xf0: /* Reset NAND Flash core */
|
||||
onenand_reset(s, 0);
|
||||
break;
|
||||
case 0xf3: /* Reset OneNAND */
|
||||
case 0xf3: /* Reset OneNAND */
|
||||
onenand_reset(s, 0);
|
||||
break;
|
||||
|
||||
case 0x65: /* OTP Access */
|
||||
case 0x65: /* OTP Access */
|
||||
s->intstatus |= ONEN_INT;
|
||||
s->blk_cur = NULL;
|
||||
s->current = s->otp;
|
||||
|
|
@ -616,52 +616,52 @@ static uint64_t onenand_read(void *opaque, hwaddr addr,
|
|||
case 0x0000 ... 0xbffe:
|
||||
return lduw_le_p(s->boot[0] + addr);
|
||||
|
||||
case 0xf000: /* Manufacturer ID */
|
||||
case 0xf000: /* Manufacturer ID */
|
||||
return s->id.man;
|
||||
case 0xf001: /* Device ID */
|
||||
case 0xf001: /* Device ID */
|
||||
return s->id.dev;
|
||||
case 0xf002: /* Version ID */
|
||||
case 0xf002: /* Version ID */
|
||||
return s->id.ver;
|
||||
/* TODO: get the following values from a real chip! */
|
||||
case 0xf003: /* Data Buffer size */
|
||||
case 0xf003: /* Data Buffer size */
|
||||
return 1 << PAGE_SHIFT;
|
||||
case 0xf004: /* Boot Buffer size */
|
||||
case 0xf004: /* Boot Buffer size */
|
||||
return 0x200;
|
||||
case 0xf005: /* Amount of buffers */
|
||||
case 0xf005: /* Amount of buffers */
|
||||
return 1 | (2 << 8);
|
||||
case 0xf006: /* Technology */
|
||||
case 0xf006: /* Technology */
|
||||
return 0;
|
||||
|
||||
case 0xf100 ... 0xf107: /* Start addresses */
|
||||
case 0xf100 ... 0xf107: /* Start addresses */
|
||||
return s->addr[offset - 0xf100];
|
||||
|
||||
case 0xf200: /* Start buffer */
|
||||
case 0xf200: /* Start buffer */
|
||||
return (s->bufaddr << 8) | ((s->count - 1) & (1 << (PAGE_SHIFT - 10)));
|
||||
|
||||
case 0xf220: /* Command */
|
||||
case 0xf220: /* Command */
|
||||
return s->command;
|
||||
case 0xf221: /* System Configuration 1 */
|
||||
case 0xf221: /* System Configuration 1 */
|
||||
return s->config[0] & 0xffe0;
|
||||
case 0xf222: /* System Configuration 2 */
|
||||
case 0xf222: /* System Configuration 2 */
|
||||
return s->config[1];
|
||||
|
||||
case 0xf240: /* Controller Status */
|
||||
case 0xf240: /* Controller Status */
|
||||
return s->status;
|
||||
case 0xf241: /* Interrupt */
|
||||
case 0xf241: /* Interrupt */
|
||||
return s->intstatus;
|
||||
case 0xf24c: /* Unlock Start Block Address */
|
||||
case 0xf24c: /* Unlock Start Block Address */
|
||||
return s->unladdr[0];
|
||||
case 0xf24d: /* Unlock End Block Address */
|
||||
case 0xf24d: /* Unlock End Block Address */
|
||||
return s->unladdr[1];
|
||||
case 0xf24e: /* Write Protection Status */
|
||||
case 0xf24e: /* Write Protection Status */
|
||||
return s->wpstatus;
|
||||
|
||||
case 0xff00: /* ECC Status */
|
||||
case 0xff00: /* ECC Status */
|
||||
return 0x00;
|
||||
case 0xff01: /* ECC Result of main area data */
|
||||
case 0xff02: /* ECC Result of spare area data */
|
||||
case 0xff03: /* ECC Result of main area data */
|
||||
case 0xff04: /* ECC Result of spare area data */
|
||||
case 0xff01: /* ECC Result of main area data */
|
||||
case 0xff02: /* ECC Result of spare area data */
|
||||
case 0xff03: /* ECC Result of main area data */
|
||||
case 0xff04: /* ECC Result of spare area data */
|
||||
qemu_log_mask(LOG_UNIMP,
|
||||
"onenand: ECC result registers unimplemented\n");
|
||||
return 0x0000;
|
||||
|
|
@ -696,15 +696,15 @@ static void onenand_write(void *opaque, hwaddr addr,
|
|||
}
|
||||
|
||||
switch (value) {
|
||||
case 0x00f0: /* Reset OneNAND */
|
||||
case 0x00f0: /* Reset OneNAND */
|
||||
onenand_reset(s, 0);
|
||||
break;
|
||||
|
||||
case 0x00e0: /* Load Data into Buffer */
|
||||
case 0x00e0: /* Load Data into Buffer */
|
||||
s->cycle = 1;
|
||||
break;
|
||||
|
||||
case 0x0090: /* Read Identification Data */
|
||||
case 0x0090: /* Read Identification Data */
|
||||
memset(s->boot[0], 0, 3 << s->shift);
|
||||
s->boot[0][0 << s->shift] = s->id.man & 0xff;
|
||||
s->boot[0][1 << s->shift] = s->id.dev & 0xff;
|
||||
|
|
@ -718,11 +718,11 @@ static void onenand_write(void *opaque, hwaddr addr,
|
|||
}
|
||||
break;
|
||||
|
||||
case 0xf100 ... 0xf107: /* Start addresses */
|
||||
case 0xf100 ... 0xf107: /* Start addresses */
|
||||
s->addr[offset - 0xf100] = value;
|
||||
break;
|
||||
|
||||
case 0xf200: /* Start buffer */
|
||||
case 0xf200: /* Start buffer */
|
||||
s->bufaddr = (value >> 8) & 0xf;
|
||||
if (PAGE_SHIFT == 11)
|
||||
s->count = (value & 3) ?: 4;
|
||||
|
|
@ -730,36 +730,36 @@ static void onenand_write(void *opaque, hwaddr addr,
|
|||
s->count = (value & 1) ?: 2;
|
||||
break;
|
||||
|
||||
case 0xf220: /* Command */
|
||||
case 0xf220: /* Command */
|
||||
if (s->intstatus & (1 << 15))
|
||||
break;
|
||||
s->command = value;
|
||||
onenand_command(s);
|
||||
break;
|
||||
case 0xf221: /* System Configuration 1 */
|
||||
case 0xf221: /* System Configuration 1 */
|
||||
s->config[0] = value;
|
||||
onenand_intr_update(s);
|
||||
qemu_set_irq(s->rdy, (s->config[0] >> 7) & 1);
|
||||
break;
|
||||
case 0xf222: /* System Configuration 2 */
|
||||
case 0xf222: /* System Configuration 2 */
|
||||
s->config[1] = value;
|
||||
break;
|
||||
|
||||
case 0xf241: /* Interrupt */
|
||||
case 0xf241: /* Interrupt */
|
||||
s->intstatus &= value;
|
||||
if ((1 << 15) & ~s->intstatus)
|
||||
s->status &= ~(ONEN_ERR_CMD | ONEN_ERR_ERASE |
|
||||
ONEN_ERR_PROG | ONEN_ERR_LOAD);
|
||||
onenand_intr_update(s);
|
||||
break;
|
||||
case 0xf24c: /* Unlock Start Block Address */
|
||||
case 0xf24c: /* Unlock Start Block Address */
|
||||
s->unladdr[0] = value & (s->blocks - 1);
|
||||
/* For some reason we have to set the end address to by default
|
||||
* be same as start because the software forgets to write anything
|
||||
* in there. */
|
||||
s->unladdr[1] = value & (s->blocks - 1);
|
||||
break;
|
||||
case 0xf24d: /* Unlock End Block Address */
|
||||
case 0xf24d: /* Unlock End Block Address */
|
||||
s->unladdr[1] = value & (s->blocks - 1);
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -62,24 +62,24 @@ static void init_dev(tc58128_dev * dev, const char *filename)
|
|||
dev->flash_contents = g_malloc(FLASH_SIZE);
|
||||
memset(dev->flash_contents, 0xff, FLASH_SIZE);
|
||||
if (filename) {
|
||||
/* Load flash image skipping the first block */
|
||||
/* Load flash image skipping the first block */
|
||||
ret = load_image_size(filename, dev->flash_contents + 528 * 32,
|
||||
FLASH_SIZE - 528 * 32);
|
||||
if (ret < 0) {
|
||||
if (ret < 0) {
|
||||
if (!qtest_enabled()) {
|
||||
error_report("Could not load flash image %s", filename);
|
||||
exit(1);
|
||||
}
|
||||
} else {
|
||||
/* Build first block with number of blocks */
|
||||
} else {
|
||||
/* Build first block with number of blocks */
|
||||
blocks = DIV_ROUND_UP(ret, 528 * 32);
|
||||
dev->flash_contents[0] = blocks & 0xff;
|
||||
dev->flash_contents[1] = (blocks >> 8) & 0xff;
|
||||
dev->flash_contents[2] = (blocks >> 16) & 0xff;
|
||||
dev->flash_contents[3] = (blocks >> 24) & 0xff;
|
||||
fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
|
||||
filename);
|
||||
}
|
||||
dev->flash_contents[0] = blocks & 0xff;
|
||||
dev->flash_contents[1] = (blocks >> 8) & 0xff;
|
||||
dev->flash_contents[2] = (blocks >> 16) & 0xff;
|
||||
dev->flash_contents[3] = (blocks >> 24) & 0xff;
|
||||
fprintf(stderr, "loaded %d bytes for %s into flash\n", ret,
|
||||
filename);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -87,26 +87,26 @@ static void handle_command(tc58128_dev * dev, uint8_t command)
|
|||
{
|
||||
switch (command) {
|
||||
case 0xff:
|
||||
fprintf(stderr, "reset flash device\n");
|
||||
dev->state = WAIT;
|
||||
break;
|
||||
fprintf(stderr, "reset flash device\n");
|
||||
dev->state = WAIT;
|
||||
break;
|
||||
case 0x00:
|
||||
fprintf(stderr, "read mode 1\n");
|
||||
dev->state = READ1;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
fprintf(stderr, "read mode 1\n");
|
||||
dev->state = READ1;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
case 0x01:
|
||||
fprintf(stderr, "read mode 2\n");
|
||||
dev->state = READ2;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
fprintf(stderr, "read mode 2\n");
|
||||
dev->state = READ2;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
case 0x50:
|
||||
fprintf(stderr, "read mode 3\n");
|
||||
dev->state = READ3;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
fprintf(stderr, "read mode 3\n");
|
||||
dev->state = READ3;
|
||||
dev->address_cycle = 0;
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "unknown flash command 0x%02x\n", command);
|
||||
fprintf(stderr, "unknown flash command 0x%02x\n", command);
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
|
@ -117,28 +117,28 @@ static void handle_address(tc58128_dev * dev, uint8_t data)
|
|||
case READ1:
|
||||
case READ2:
|
||||
case READ3:
|
||||
switch (dev->address_cycle) {
|
||||
case 0:
|
||||
dev->address = data;
|
||||
if (dev->state == READ2)
|
||||
dev->address |= 0x100;
|
||||
else if (dev->state == READ3)
|
||||
dev->address |= 0x200;
|
||||
break;
|
||||
case 1:
|
||||
dev->address += data * 528 * 0x100;
|
||||
break;
|
||||
case 2:
|
||||
dev->address += data * 528;
|
||||
fprintf(stderr, "address pointer in flash: 0x%08x\n",
|
||||
dev->address);
|
||||
break;
|
||||
default:
|
||||
/* Invalid data */
|
||||
switch (dev->address_cycle) {
|
||||
case 0:
|
||||
dev->address = data;
|
||||
if (dev->state == READ2)
|
||||
dev->address |= 0x100;
|
||||
else if (dev->state == READ3)
|
||||
dev->address |= 0x200;
|
||||
break;
|
||||
case 1:
|
||||
dev->address += data * 528 * 0x100;
|
||||
break;
|
||||
case 2:
|
||||
dev->address += data * 528;
|
||||
fprintf(stderr, "address pointer in flash: 0x%08x\n",
|
||||
dev->address);
|
||||
break;
|
||||
default:
|
||||
/* Invalid data */
|
||||
abort();
|
||||
}
|
||||
dev->address_cycle++;
|
||||
break;
|
||||
}
|
||||
dev->address_cycle++;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
|
|
@ -148,7 +148,7 @@ static uint8_t handle_read(tc58128_dev * dev)
|
|||
{
|
||||
#if 0
|
||||
if (dev->address % 0x100000 == 0)
|
||||
fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
|
||||
fprintf(stderr, "reading flash at address 0x%08x\n", dev->address);
|
||||
#endif
|
||||
return dev->flash_contents[dev->address++];
|
||||
}
|
||||
|
|
@ -163,31 +163,31 @@ static int tc58128_cb(uint16_t porta, uint16_t portb,
|
|||
int dev;
|
||||
|
||||
if ((porta & CE1) == 0)
|
||||
dev = 0;
|
||||
dev = 0;
|
||||
else if ((porta & CE2) == 0)
|
||||
dev = 1;
|
||||
dev = 1;
|
||||
else
|
||||
return 0; /* No device selected */
|
||||
return 0; /* No device selected */
|
||||
|
||||
if ((porta & RE) && (porta & WE)) {
|
||||
/* Nothing to do, assert ready and return to input state */
|
||||
*periph_portadir &= 0xff00;
|
||||
*periph_portadir |= RDY(dev);
|
||||
*periph_pdtra |= RDY(dev);
|
||||
return 1;
|
||||
/* Nothing to do, assert ready and return to input state */
|
||||
*periph_portadir &= 0xff00;
|
||||
*periph_portadir |= RDY(dev);
|
||||
*periph_pdtra |= RDY(dev);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (porta & CLE) {
|
||||
/* Command */
|
||||
assert((porta & WE) == 0);
|
||||
handle_command(&tc58128_devs[dev], porta & 0x00ff);
|
||||
/* Command */
|
||||
assert((porta & WE) == 0);
|
||||
handle_command(&tc58128_devs[dev], porta & 0x00ff);
|
||||
} else if (porta & ALE) {
|
||||
assert((porta & WE) == 0);
|
||||
handle_address(&tc58128_devs[dev], porta & 0x00ff);
|
||||
assert((porta & WE) == 0);
|
||||
handle_address(&tc58128_devs[dev], porta & 0x00ff);
|
||||
} else if ((porta & RE) == 0) {
|
||||
*periph_portadir |= 0x00ff;
|
||||
*periph_pdtra &= 0xff00;
|
||||
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
|
||||
*periph_portadir |= 0x00ff;
|
||||
*periph_pdtra &= 0xff00;
|
||||
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
|
||||
} else {
|
||||
abort();
|
||||
}
|
||||
|
|
@ -195,9 +195,9 @@ static int tc58128_cb(uint16_t porta, uint16_t portb,
|
|||
}
|
||||
|
||||
static sh7750_io_device tc58128 = {
|
||||
RE | WE, /* Port A triggers */
|
||||
0, /* Port B triggers */
|
||||
tc58128_cb /* Callback */
|
||||
RE | WE, /* Port A triggers */
|
||||
0, /* Port B triggers */
|
||||
tc58128_cb /* Callback */
|
||||
};
|
||||
|
||||
int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2)
|
||||
|
|
|
|||
|
|
@ -53,22 +53,22 @@ void nand_setio(DeviceState *dev, uint32_t value);
|
|||
uint32_t nand_getio(DeviceState *dev);
|
||||
uint32_t nand_getbuswidth(DeviceState *dev);
|
||||
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
#define NAND_MFR_FUJITSU 0x04
|
||||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
#define NAND_MFR_TOSHIBA 0x98
|
||||
#define NAND_MFR_SAMSUNG 0xec
|
||||
#define NAND_MFR_FUJITSU 0x04
|
||||
#define NAND_MFR_NATIONAL 0x8f
|
||||
#define NAND_MFR_RENESAS 0x07
|
||||
#define NAND_MFR_STMICRO 0x20
|
||||
#define NAND_MFR_HYNIX 0xad
|
||||
#define NAND_MFR_MICRON 0x2c
|
||||
|
||||
/* onenand.c */
|
||||
void *onenand_raw_otp(DeviceState *onenand_device);
|
||||
|
||||
/* ecc.c */
|
||||
typedef struct {
|
||||
uint8_t cp; /* Column parity */
|
||||
uint16_t lp[2]; /* Line parity */
|
||||
uint8_t cp; /* Column parity */
|
||||
uint16_t lp[2]; /* Line parity */
|
||||
uint16_t count;
|
||||
} ECCState;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue