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hw/intc/armv7m_nvic: add "num-prio-bits" property

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Cortex-M NVIC can have a different number of priority bits.
Cortex-M0/M0+/M1 devices must use 2 or more bits, while devices based
on ARMv7m and up must use 3 or more bits.

This adds a "num-prio-bits" property which will get sensible default
values if unset (2 or 8 depending on the device). Unless a SOC
specifies the number of bits to use, the previous behavior is
maintained for backward compatibility.

Signed-off-by: Samuel Tardieu <sam@rfc1149.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240106181503.1746200-2-sam@rfc1149.net
Suggested-by: Anton Kochkov <anton.kochkov@proton.me>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1122
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Samuel Tardieu 2024-01-06 19:15:01 +01:00 committed by Peter Maydell
parent 41581f1361
commit d09923ad19
1 changed files with 22 additions and 1 deletions
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23
hw/intc/armv7m_nvic.c
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@ -2572,6 +2572,11 @@ static const VMStateDescription vmstate_nvic = {
static Property props_nvic[] = { static Property props_nvic[] = {
/* Number of external IRQ lines (so excluding the 16 internal exceptions) */ /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64), DEFINE_PROP_UINT32("num-irq", NVICState, num_irq, 64),
/*
* Number of the maximum priority bits that can be used. 0 means
* to use a reasonable default.
*/
DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };
@ -2685,7 +2690,23 @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
/* include space for internal exception vectors */ /* include space for internal exception vectors */
s->num_irq += NVIC_FIRST_IRQ; s->num_irq += NVIC_FIRST_IRQ;
s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2; if (s->num_prio_bits == 0) {
/*
* If left unspecified, use 2 bits by default on Cortex-M0/M0+/M1
* and 8 bits otherwise.
*/
s->num_prio_bits = arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 8 : 2;
} else {
uint8_t min_prio_bits =
arm_feature(&s->cpu->env, ARM_FEATURE_V7) ? 3 : 2;
if (s->num_prio_bits < min_prio_bits || s->num_prio_bits > 8) {
error_setg(errp,
"num-prio-bits %d is outside "
"NVIC acceptable range [%d-8]",
s->num_prio_bits, min_prio_bits);
return;
}
}
/* /*
* This device provides a single memory region which covers the * This device provides a single memory region which covers the