i8254: Factor out base class for KVM reuse
Applying the concept used for the *PICs once again: establish a base class for the i8254 that can be used both by the current user space emulation and the upcoming KVM in-kernel version. We share most of the public interface of the i8254, specifically to the pcspk, vmstate, reset and certain init parts. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
e32605062c
commit
d11e859e4a
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@ -210,7 +210,7 @@ hw-obj-$(CONFIG_EMPTY_SLOT) += empty_slot.o
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hw-obj-$(CONFIG_SERIAL) += serial.o
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hw-obj-$(CONFIG_SERIAL) += serial.o
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hw-obj-$(CONFIG_PARALLEL) += parallel.o
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hw-obj-$(CONFIG_PARALLEL) += parallel.o
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hw-obj-$(CONFIG_I8254) += i8254.o
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hw-obj-$(CONFIG_I8254) += i8254_common.o i8254.o
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hw-obj-$(CONFIG_PCSPK) += pcspk.o
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hw-obj-$(CONFIG_PCSPK) += pcspk.o
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hw-obj-$(CONFIG_PCKBD) += pckbd.o
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hw-obj-$(CONFIG_PCKBD) += pckbd.o
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hw-obj-$(CONFIG_USB_UHCI) += usb-uhci.o
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hw-obj-$(CONFIG_USB_UHCI) += usb-uhci.o
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267
hw/i8254.c
267
hw/i8254.c
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@ -26,6 +26,7 @@
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#include "isa.h"
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#include "isa.h"
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#include "qemu-timer.h"
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#include "qemu-timer.h"
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#include "i8254.h"
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#include "i8254.h"
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#include "i8254_internal.h"
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//#define DEBUG_PIT
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//#define DEBUG_PIT
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@ -34,34 +35,6 @@
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD1 4
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#define RW_STATE_WORD1 4
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typedef struct PITChannelState {
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int count; /* can be 65536 */
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uint16_t latched_count;
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uint8_t count_latched;
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uint8_t status_latched;
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uint8_t status;
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uint8_t read_state;
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uint8_t write_state;
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uint8_t write_latch;
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uint8_t rw_mode;
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uint8_t mode;
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uint8_t bcd; /* not supported */
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uint8_t gate; /* timer start */
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int64_t count_load_time;
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/* irq handling */
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int64_t next_transition_time;
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QEMUTimer *irq_timer;
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qemu_irq irq;
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uint32_t irq_disabled;
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} PITChannelState;
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typedef struct PITState {
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ISADevice dev;
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MemoryRegion ioports;
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uint32_t iobase;
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PITChannelState channels[3];
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} PITState;
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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static int pit_get_count(PITChannelState *s)
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@ -89,99 +62,11 @@ static int pit_get_count(PITChannelState *s)
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return counter;
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return counter;
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}
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}
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/* get pit output bit */
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static int pit_get_out(PITChannelState *s, int64_t current_time)
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{
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uint64_t d;
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int out;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
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get_ticks_per_sec());
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switch(s->mode) {
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default:
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case 0:
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out = (d >= s->count);
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break;
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case 1:
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out = (d < s->count);
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break;
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case 2:
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if ((d % s->count) == 0 && d != 0)
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out = 1;
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else
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out = 0;
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break;
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case 3:
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out = (d % s->count) < ((s->count + 1) >> 1);
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break;
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case 4:
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case 5:
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out = (d == s->count);
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break;
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}
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return out;
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}
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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{
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uint64_t d, next_time, base;
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int period2;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
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get_ticks_per_sec());
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switch(s->mode) {
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default:
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case 0:
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case 1:
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if (d < s->count)
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next_time = s->count;
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else
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return -1;
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break;
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case 2:
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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else
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next_time = base + s->count + 1;
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break;
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case 3:
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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if ((d - base) < period2)
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next_time = base + period2;
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else
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next_time = base + s->count;
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break;
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case 4:
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case 5:
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if (d < s->count)
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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else
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return -1;
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break;
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}
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
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PIT_FREQ);
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/* fix potential rounding problems */
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/* XXX: better solution: use a clock at PIT_FREQ Hz */
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if (next_time <= current_time)
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next_time = current_time + 1;
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return next_time;
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}
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/* val must be 0 or 1 */
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/* val must be 0 or 1 */
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void pit_set_gate(ISADevice *dev, int channel, int val)
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static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
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int val)
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{
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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switch (sc->mode) {
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PITChannelState *s = &pit->channels[channel];
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switch(s->mode) {
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default:
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default:
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case 0:
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case 0:
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case 4:
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case 4:
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@ -189,34 +74,23 @@ void pit_set_gate(ISADevice *dev, int channel, int val)
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break;
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break;
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case 1:
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case 1:
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case 5:
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case 5:
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if (s->gate < val) {
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if (sc->gate < val) {
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/* restart counting on rising edge */
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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sc->count_load_time = qemu_get_clock_ns(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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pit_irq_timer_update(sc, sc->count_load_time);
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}
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}
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break;
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break;
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case 2:
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case 2:
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case 3:
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case 3:
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if (s->gate < val) {
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if (sc->gate < val) {
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/* restart counting on rising edge */
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/* restart counting on rising edge */
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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sc->count_load_time = qemu_get_clock_ns(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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pit_irq_timer_update(sc, sc->count_load_time);
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}
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}
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/* XXX: disable/enable counting */
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/* XXX: disable/enable counting */
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break;
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break;
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}
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}
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s->gate = val;
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sc->gate = val;
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}
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void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s = &pit->channels[channel];
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info->gate = s->gate;
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info->mode = s->mode;
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info->initial_count = s->count;
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info->out = pit_get_out(s, qemu_get_clock_ns(vm_clock));
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}
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}
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static inline void pit_load_count(PITChannelState *s, int val)
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static inline void pit_load_count(PITChannelState *s, int val)
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@ -239,7 +113,7 @@ static void pit_latch_count(PITChannelState *s)
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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{
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PITState *pit = opaque;
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PITCommonState *pit = opaque;
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int channel, access;
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int channel, access;
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PITChannelState *s;
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PITChannelState *s;
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@ -306,7 +180,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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{
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{
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PITState *pit = opaque;
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PITCommonState *pit = opaque;
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int ret, count;
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int ret, count;
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PITChannelState *s;
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PITChannelState *s;
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pit_irq_timer_update(s, s->next_transition_time);
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pit_irq_timer_update(s, s->next_transition_time);
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}
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}
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static const VMStateDescription vmstate_pit_channel = {
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.name = "pit channel",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField []) {
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VMSTATE_INT32(count, PITChannelState),
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VMSTATE_UINT16(latched_count, PITChannelState),
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VMSTATE_UINT8(count_latched, PITChannelState),
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VMSTATE_UINT8(status_latched, PITChannelState),
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VMSTATE_UINT8(status, PITChannelState),
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VMSTATE_UINT8(read_state, PITChannelState),
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VMSTATE_UINT8(write_state, PITChannelState),
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VMSTATE_UINT8(write_latch, PITChannelState),
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VMSTATE_UINT8(rw_mode, PITChannelState),
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VMSTATE_UINT8(mode, PITChannelState),
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VMSTATE_UINT8(bcd, PITChannelState),
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VMSTATE_UINT8(gate, PITChannelState),
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VMSTATE_INT64(count_load_time, PITChannelState),
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VMSTATE_INT64(next_transition_time, PITChannelState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
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{
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PITState *pit = opaque;
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PITChannelState *s;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for(i = 0; i < 3; i++) {
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s = &pit->channels[i];
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s->count=qemu_get_be32(f);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->count_latched);
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qemu_get_8s(f, &s->status_latched);
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qemu_get_8s(f, &s->status);
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qemu_get_8s(f, &s->read_state);
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qemu_get_8s(f, &s->write_state);
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qemu_get_8s(f, &s->write_latch);
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qemu_get_8s(f, &s->rw_mode);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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s->count_load_time=qemu_get_be64(f);
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s->irq_disabled = 0;
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if (s->irq_timer) {
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s->next_transition_time=qemu_get_be64(f);
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qemu_get_timer(f, s->irq_timer);
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}
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}
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return 0;
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}
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static const VMStateDescription vmstate_pit = {
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.name = "i8254",
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.version_id = 3,
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.minimum_version_id = 2,
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.minimum_version_id_old = 1,
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.load_state_old = pit_load_old,
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.fields = (VMStateField []) {
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VMSTATE_UINT32_V(channels[0].irq_disabled, PITState, 3),
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VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState),
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VMSTATE_TIMER(channels[0].irq_timer, PITState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pit_reset(DeviceState *dev)
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static void pit_reset(DeviceState *dev)
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{
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{
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PITState *pit = container_of(dev, PITState, dev.qdev);
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PITCommonState *pit = DO_UPCAST(PITCommonState, dev.qdev, dev);
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PITChannelState *s;
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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pit_reset_common(pit);
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s = &pit->channels[i];
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s->mode = 3;
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s = &pit->channels[0];
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s->gate = (i != 2);
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if (!s->irq_disabled) {
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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s->count = 0x10000;
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if (i == 0 && !s->irq_disabled) {
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s->next_transition_time =
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pit_get_next_transition_time(s, s->count_load_time);
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qemu_mod_timer(s->irq_timer, s->next_transition_time);
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qemu_mod_timer(s->irq_timer, s->next_transition_time);
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}
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}
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}
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}
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}
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/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
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/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
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* reenable it when legacy mode is left again. */
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* reenable it when legacy mode is left again. */
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static void pit_irq_control(void *opaque, int n, int enable)
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static void pit_irq_control(void *opaque, int n, int enable)
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{
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{
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PITState *pit = opaque;
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PITCommonState *pit = opaque;
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PITChannelState *s = &pit->channels[0];
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PITChannelState *s = &pit->channels[0];
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if (enable) {
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if (enable) {
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@ -504,46 +300,43 @@ static const MemoryRegionOps pit_ioport_ops = {
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.old_portio = pit_portio
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.old_portio = pit_portio
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};
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};
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static int pit_initfn(ISADevice *dev)
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static int pit_initfn(PITCommonState *pit)
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{
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{
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PITState *pit = DO_UPCAST(PITState, dev, dev);
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PITChannelState *s;
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PITChannelState *s;
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s = &pit->channels[0];
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s = &pit->channels[0];
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/* the timer 0 is connected to an IRQ */
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
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s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
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qdev_init_gpio_out(&dev->qdev, &s->irq, 1);
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qdev_init_gpio_out(&pit->dev.qdev, &s->irq, 1);
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memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
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memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
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isa_register_ioport(dev, &pit->ioports, pit->iobase);
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|
||||||
qdev_init_gpio_in(&dev->qdev, pit_irq_control, 1);
|
qdev_init_gpio_in(&pit->dev.qdev, pit_irq_control, 1);
|
||||||
|
|
||||||
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static Property pit_properties[] = {
|
static Property pit_properties[] = {
|
||||||
DEFINE_PROP_HEX32("iobase", PITState, iobase, -1),
|
DEFINE_PROP_HEX32("iobase", PITCommonState, iobase, -1),
|
||||||
DEFINE_PROP_END_OF_LIST(),
|
DEFINE_PROP_END_OF_LIST(),
|
||||||
};
|
};
|
||||||
|
|
||||||
static void pit_class_initfn(ObjectClass *klass, void *data)
|
static void pit_class_initfn(ObjectClass *klass, void *data)
|
||||||
{
|
{
|
||||||
|
PITCommonClass *k = PIT_COMMON_CLASS(klass);
|
||||||
DeviceClass *dc = DEVICE_CLASS(klass);
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
|
|
||||||
ic->init = pit_initfn;
|
k->init = pit_initfn;
|
||||||
dc->no_user = 1;
|
k->set_channel_gate = pit_set_channel_gate;
|
||||||
|
k->get_channel_info = pit_get_channel_info_common;
|
||||||
dc->reset = pit_reset;
|
dc->reset = pit_reset;
|
||||||
dc->vmsd = &vmstate_pit;
|
|
||||||
dc->props = pit_properties;
|
dc->props = pit_properties;
|
||||||
}
|
}
|
||||||
|
|
||||||
static TypeInfo pit_info = {
|
static TypeInfo pit_info = {
|
||||||
.name = "isa-pit",
|
.name = "isa-pit",
|
||||||
.parent = TYPE_ISA_DEVICE,
|
.parent = TYPE_PIT_COMMON,
|
||||||
.instance_size = sizeof(PITState),
|
.instance_size = sizeof(PITCommonState),
|
||||||
.class_init = pit_class_initfn,
|
.class_init = pit_class_initfn,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
|
@ -0,0 +1,307 @@
|
||||||
|
/*
|
||||||
|
* QEMU 8253/8254 - common bits of emulated and KVM kernel model
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
* Copyright (c) 2012 Jan Kiszka, Siemens AG
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "hw.h"
|
||||||
|
#include "pc.h"
|
||||||
|
#include "isa.h"
|
||||||
|
#include "qemu-timer.h"
|
||||||
|
#include "i8254.h"
|
||||||
|
#include "i8254_internal.h"
|
||||||
|
|
||||||
|
/* val must be 0 or 1 */
|
||||||
|
void pit_set_gate(ISADevice *dev, int channel, int val)
|
||||||
|
{
|
||||||
|
PITCommonState *pit = PIT_COMMON(dev);
|
||||||
|
PITChannelState *s = &pit->channels[channel];
|
||||||
|
PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
|
||||||
|
|
||||||
|
c->set_channel_gate(pit, s, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* get pit output bit */
|
||||||
|
int pit_get_out(PITChannelState *s, int64_t current_time)
|
||||||
|
{
|
||||||
|
uint64_t d;
|
||||||
|
int out;
|
||||||
|
|
||||||
|
d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
|
||||||
|
get_ticks_per_sec());
|
||||||
|
switch (s->mode) {
|
||||||
|
default:
|
||||||
|
case 0:
|
||||||
|
out = (d >= s->count);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
out = (d < s->count);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
if ((d % s->count) == 0 && d != 0) {
|
||||||
|
out = 1;
|
||||||
|
} else {
|
||||||
|
out = 0;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
out = (d % s->count) < ((s->count + 1) >> 1);
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
case 5:
|
||||||
|
out = (d == s->count);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
return out;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* return -1 if no transition will occur. */
|
||||||
|
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time)
|
||||||
|
{
|
||||||
|
uint64_t d, next_time, base;
|
||||||
|
int period2;
|
||||||
|
|
||||||
|
d = muldiv64(current_time - s->count_load_time, PIT_FREQ,
|
||||||
|
get_ticks_per_sec());
|
||||||
|
switch (s->mode) {
|
||||||
|
default:
|
||||||
|
case 0:
|
||||||
|
case 1:
|
||||||
|
if (d < s->count) {
|
||||||
|
next_time = s->count;
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
base = (d / s->count) * s->count;
|
||||||
|
if ((d - base) == 0 && d != 0) {
|
||||||
|
next_time = base + s->count;
|
||||||
|
} else {
|
||||||
|
next_time = base + s->count + 1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 3:
|
||||||
|
base = (d / s->count) * s->count;
|
||||||
|
period2 = ((s->count + 1) >> 1);
|
||||||
|
if ((d - base) < period2) {
|
||||||
|
next_time = base + period2;
|
||||||
|
} else {
|
||||||
|
next_time = base + s->count;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 4:
|
||||||
|
case 5:
|
||||||
|
if (d < s->count) {
|
||||||
|
next_time = s->count;
|
||||||
|
} else if (d == s->count) {
|
||||||
|
next_time = s->count + 1;
|
||||||
|
} else {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
/* convert to timer units */
|
||||||
|
next_time = s->count_load_time + muldiv64(next_time, get_ticks_per_sec(),
|
||||||
|
PIT_FREQ);
|
||||||
|
/* fix potential rounding problems */
|
||||||
|
/* XXX: better solution: use a clock at PIT_FREQ Hz */
|
||||||
|
if (next_time <= current_time) {
|
||||||
|
next_time = current_time + 1;
|
||||||
|
}
|
||||||
|
return next_time;
|
||||||
|
}
|
||||||
|
|
||||||
|
void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
|
||||||
|
PITChannelInfo *info)
|
||||||
|
{
|
||||||
|
info->gate = sc->gate;
|
||||||
|
info->mode = sc->mode;
|
||||||
|
info->initial_count = sc->count;
|
||||||
|
info->out = pit_get_out(sc, qemu_get_clock_ns(vm_clock));
|
||||||
|
}
|
||||||
|
|
||||||
|
void pit_get_channel_info(ISADevice *dev, int channel, PITChannelInfo *info)
|
||||||
|
{
|
||||||
|
PITCommonState *pit = PIT_COMMON(dev);
|
||||||
|
PITChannelState *s = &pit->channels[channel];
|
||||||
|
PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
|
||||||
|
|
||||||
|
c->get_channel_info(pit, s, info);
|
||||||
|
}
|
||||||
|
|
||||||
|
void pit_reset_common(PITCommonState *pit)
|
||||||
|
{
|
||||||
|
PITChannelState *s;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for (i = 0; i < 3; i++) {
|
||||||
|
s = &pit->channels[i];
|
||||||
|
s->mode = 3;
|
||||||
|
s->gate = (i != 2);
|
||||||
|
s->count_load_time = qemu_get_clock_ns(vm_clock);
|
||||||
|
s->count = 0x10000;
|
||||||
|
if (i == 0 && !s->irq_disabled) {
|
||||||
|
s->next_transition_time =
|
||||||
|
pit_get_next_transition_time(s, s->count_load_time);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int pit_init_common(ISADevice *dev)
|
||||||
|
{
|
||||||
|
PITCommonState *pit = PIT_COMMON(dev);
|
||||||
|
PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
|
||||||
|
int ret;
|
||||||
|
|
||||||
|
ret = c->init(pit);
|
||||||
|
if (ret < 0) {
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
isa_register_ioport(dev, &pit->ioports, pit->iobase);
|
||||||
|
|
||||||
|
qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_pit_channel = {
|
||||||
|
.name = "pit channel",
|
||||||
|
.version_id = 2,
|
||||||
|
.minimum_version_id = 2,
|
||||||
|
.minimum_version_id_old = 2,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_INT32(count, PITChannelState),
|
||||||
|
VMSTATE_UINT16(latched_count, PITChannelState),
|
||||||
|
VMSTATE_UINT8(count_latched, PITChannelState),
|
||||||
|
VMSTATE_UINT8(status_latched, PITChannelState),
|
||||||
|
VMSTATE_UINT8(status, PITChannelState),
|
||||||
|
VMSTATE_UINT8(read_state, PITChannelState),
|
||||||
|
VMSTATE_UINT8(write_state, PITChannelState),
|
||||||
|
VMSTATE_UINT8(write_latch, PITChannelState),
|
||||||
|
VMSTATE_UINT8(rw_mode, PITChannelState),
|
||||||
|
VMSTATE_UINT8(mode, PITChannelState),
|
||||||
|
VMSTATE_UINT8(bcd, PITChannelState),
|
||||||
|
VMSTATE_UINT8(gate, PITChannelState),
|
||||||
|
VMSTATE_INT64(count_load_time, PITChannelState),
|
||||||
|
VMSTATE_INT64(next_transition_time, PITChannelState),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
|
||||||
|
{
|
||||||
|
PITCommonState *pit = opaque;
|
||||||
|
PITChannelState *s;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
if (version_id != 1) {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < 3; i++) {
|
||||||
|
s = &pit->channels[i];
|
||||||
|
s->count = qemu_get_be32(f);
|
||||||
|
qemu_get_be16s(f, &s->latched_count);
|
||||||
|
qemu_get_8s(f, &s->count_latched);
|
||||||
|
qemu_get_8s(f, &s->status_latched);
|
||||||
|
qemu_get_8s(f, &s->status);
|
||||||
|
qemu_get_8s(f, &s->read_state);
|
||||||
|
qemu_get_8s(f, &s->write_state);
|
||||||
|
qemu_get_8s(f, &s->write_latch);
|
||||||
|
qemu_get_8s(f, &s->rw_mode);
|
||||||
|
qemu_get_8s(f, &s->mode);
|
||||||
|
qemu_get_8s(f, &s->bcd);
|
||||||
|
qemu_get_8s(f, &s->gate);
|
||||||
|
s->count_load_time = qemu_get_be64(f);
|
||||||
|
s->irq_disabled = 0;
|
||||||
|
if (s->irq_timer) {
|
||||||
|
s->next_transition_time = qemu_get_be64(f);
|
||||||
|
qemu_get_timer(f, s->irq_timer);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pit_dispatch_pre_save(void *opaque)
|
||||||
|
{
|
||||||
|
PITCommonState *s = opaque;
|
||||||
|
PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
|
||||||
|
|
||||||
|
if (c->pre_save) {
|
||||||
|
c->pre_save(s);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static int pit_dispatch_post_load(void *opaque, int version_id)
|
||||||
|
{
|
||||||
|
PITCommonState *s = opaque;
|
||||||
|
PITCommonClass *c = PIT_COMMON_GET_CLASS(s);
|
||||||
|
|
||||||
|
if (c->post_load) {
|
||||||
|
c->post_load(s);
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static const VMStateDescription vmstate_pit_common = {
|
||||||
|
.name = "i8254",
|
||||||
|
.version_id = 3,
|
||||||
|
.minimum_version_id = 2,
|
||||||
|
.minimum_version_id_old = 1,
|
||||||
|
.load_state_old = pit_load_old,
|
||||||
|
.pre_save = pit_dispatch_pre_save,
|
||||||
|
.post_load = pit_dispatch_post_load,
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_UINT32_V(channels[0].irq_disabled, PITCommonState, 3),
|
||||||
|
VMSTATE_STRUCT_ARRAY(channels, PITCommonState, 3, 2,
|
||||||
|
vmstate_pit_channel, PITChannelState),
|
||||||
|
VMSTATE_TIMER(channels[0].irq_timer, PITCommonState),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pit_common_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
|
||||||
|
ic->init = pit_init_common;
|
||||||
|
dc->vmsd = &vmstate_pit_common;
|
||||||
|
dc->no_user = 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static TypeInfo pit_common_type = {
|
||||||
|
.name = TYPE_PIT_COMMON,
|
||||||
|
.parent = TYPE_ISA_DEVICE,
|
||||||
|
.instance_size = sizeof(PITCommonState),
|
||||||
|
.class_size = sizeof(PITCommonClass),
|
||||||
|
.class_init = pit_common_class_init,
|
||||||
|
.abstract = true,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void register_devices(void)
|
||||||
|
{
|
||||||
|
type_register_static(&pit_common_type);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(register_devices);
|
|
@ -0,0 +1,85 @@
|
||||||
|
/*
|
||||||
|
* QEMU 8253/8254 - internal interfaces
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011 Jan Kiszka, Siemens AG
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef QEMU_I8254_INTERNAL_H
|
||||||
|
#define QEMU_I8254_INTERNAL_H
|
||||||
|
|
||||||
|
#include "hw.h"
|
||||||
|
#include "pc.h"
|
||||||
|
#include "isa.h"
|
||||||
|
|
||||||
|
typedef struct PITChannelState {
|
||||||
|
int count; /* can be 65536 */
|
||||||
|
uint16_t latched_count;
|
||||||
|
uint8_t count_latched;
|
||||||
|
uint8_t status_latched;
|
||||||
|
uint8_t status;
|
||||||
|
uint8_t read_state;
|
||||||
|
uint8_t write_state;
|
||||||
|
uint8_t write_latch;
|
||||||
|
uint8_t rw_mode;
|
||||||
|
uint8_t mode;
|
||||||
|
uint8_t bcd; /* not supported */
|
||||||
|
uint8_t gate; /* timer start */
|
||||||
|
int64_t count_load_time;
|
||||||
|
/* irq handling */
|
||||||
|
int64_t next_transition_time;
|
||||||
|
QEMUTimer *irq_timer;
|
||||||
|
qemu_irq irq;
|
||||||
|
uint32_t irq_disabled;
|
||||||
|
} PITChannelState;
|
||||||
|
|
||||||
|
typedef struct PITCommonState {
|
||||||
|
ISADevice dev;
|
||||||
|
MemoryRegion ioports;
|
||||||
|
uint32_t iobase;
|
||||||
|
PITChannelState channels[3];
|
||||||
|
} PITCommonState;
|
||||||
|
|
||||||
|
#define TYPE_PIT_COMMON "pit-common"
|
||||||
|
#define PIT_COMMON(obj) \
|
||||||
|
OBJECT_CHECK(PITCommonState, (obj), TYPE_PIT_COMMON)
|
||||||
|
#define PIT_COMMON_CLASS(klass) \
|
||||||
|
OBJECT_CLASS_CHECK(PITCommonClass, (klass), TYPE_PIT_COMMON)
|
||||||
|
#define PIT_COMMON_GET_CLASS(obj) \
|
||||||
|
OBJECT_GET_CLASS(PITCommonClass, (obj), TYPE_PIT_COMMON)
|
||||||
|
|
||||||
|
typedef struct PITCommonClass {
|
||||||
|
ISADeviceClass parent_class;
|
||||||
|
|
||||||
|
int (*init)(PITCommonState *s);
|
||||||
|
void (*set_channel_gate)(PITCommonState *s, PITChannelState *sc, int val);
|
||||||
|
void (*get_channel_info)(PITCommonState *s, PITChannelState *sc,
|
||||||
|
PITChannelInfo *info);
|
||||||
|
void (*pre_save)(PITCommonState *s);
|
||||||
|
void (*post_load)(PITCommonState *s);
|
||||||
|
} PITCommonClass;
|
||||||
|
|
||||||
|
int pit_get_out(PITChannelState *s, int64_t current_time);
|
||||||
|
int64_t pit_get_next_transition_time(PITChannelState *s, int64_t current_time);
|
||||||
|
void pit_get_channel_info_common(PITCommonState *s, PITChannelState *sc,
|
||||||
|
PITChannelInfo *info);
|
||||||
|
void pit_reset_common(PITCommonState *s);
|
||||||
|
|
||||||
|
#endif /* !QEMU_I8254_INTERNAL_H */
|
Loading…
Reference in New Issue