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Clean up debugging code #ifdefs (Eduardo Habkost) 

Use macros to avoid #ifdefs on debugging code.

This patch doesn't try to merge logging macros from different files,
but just unify the debugging code #ifdefs onto a macro on each file. A
further cleanup can unify the debugging macros on a common header, later

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6332 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aliguori 2009-01-15 21:48:06 +00:00
parent 40a4539e20
commit d12d51d5ba
15 changed files with 532 additions and 963 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

313
hw/ppc.c
View File

@ -31,6 +31,25 @@
//#define PPC_DEBUG_IRQ
//#define PPC_DEBUG_TB
#ifdef PPC_DEBUG_IRQ
# define LOG_IRQ(...) do { \
if (loglevel & CPU_LOG_INT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_IRQ(...) do { } while (0)
#endif
#ifdef PPC_DEBUG_TB
# define LOG_TB(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_TB(...) do { } while (0)
#endif
static void cpu_ppc_tb_stop (CPUState *env);
static void cpu_ppc_tb_start (CPUState *env);
@ -44,13 +63,9 @@ static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
if (env->pending_interrupts == 0)
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
}
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: %p n_IRQ %d level %d => pending %08" PRIx32
LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
"req %08x\n", __func__, env, n_IRQ, level,
env->pending_interrupts, env->interrupt_request);
}
#endif
}
/* PowerPC 6xx / 7xx internal IRQ controller */
@ -59,24 +74,16 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
CPUState *env = opaque;
int cur_level;
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
}
#endif
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
case PPC6xx_INPUT_TBEN:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: %s the time base\n",
LOG_IRQ("%s: %s the time base\n",
__func__, level ? "start" : "stop");
}
#endif
if (level) {
cpu_ppc_tb_start(env);
} else {
@ -84,22 +91,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
}
case PPC6xx_INPUT_INT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the external IRQ state to %d\n",
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPC6xx_INPUT_SMI:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the SMI IRQ state to %d\n",
LOG_IRQ("%s: set the SMI IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_SMI, level);
break;
case PPC6xx_INPUT_MCP:
@ -108,12 +107,8 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
* 603/604/740/750: check HID0[EMCP]
*/
if (cur_level == 1 && level == 0) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: raise machine check state\n",
LOG_IRQ("%s: raise machine check state\n",
__func__);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
}
break;
@ -122,22 +117,14 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
/* XXX: TODO: relay the signal to CKSTP_OUT pin */
/* XXX: Note that the only way to restart the CPU is to reset it */
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: stop the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: stop the CPU\n", __func__);
env->halted = 1;
}
break;
case PPC6xx_INPUT_HRESET:
/* Level sensitive - active low */
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: reset the CPU\n", __func__);
env->interrupt_request |= CPU_INTERRUPT_EXITTB;
/* XXX: TOFIX */
#if 0
@ -148,21 +135,13 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level)
}
break;
case PPC6xx_INPUT_SRESET:
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
break;
default:
/* Unknown pin - do nothing */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
}
#endif
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
if (level)
@ -185,34 +164,22 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
CPUState *env = opaque;
int cur_level;
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
}
#endif
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
case PPC970_INPUT_INT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the external IRQ state to %d\n",
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPC970_INPUT_THINT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the SMI IRQ state to %d\n", __func__,
LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_THERM, level);
break;
case PPC970_INPUT_MCP:
@ -221,12 +188,8 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
* 603/604/740/750: check HID0[EMCP]
*/
if (cur_level == 1 && level == 0) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: raise machine check state\n",
LOG_IRQ("%s: raise machine check state\n",
__func__);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
}
break;
@ -234,18 +197,10 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active low */
/* XXX: TODO: relay the signal to CKSTP_OUT pin */
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: stop the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: stop the CPU\n", __func__);
env->halted = 1;
} else {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: restart the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: restart the CPU\n", __func__);
env->halted = 0;
}
break;
@ -253,40 +208,24 @@ static void ppc970_set_irq (void *opaque, int pin, int level)
/* Level sensitive - active low */
if (level) {
#if 0 // XXX: TOFIX
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: reset the CPU\n", __func__);
cpu_reset(env);
#endif
}
break;
case PPC970_INPUT_SRESET:
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the RESET IRQ state to %d\n",
LOG_IRQ("%s: set the RESET IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_RESET, level);
break;
case PPC970_INPUT_TBEN:
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the TBEN state to %d\n", __func__,
LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
level);
}
#endif
/* XXX: TODO */
break;
default:
/* Unknown pin - do nothing */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
}
#endif
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
if (level)
@ -309,103 +248,63 @@ static void ppc40x_set_irq (void *opaque, int pin, int level)
CPUState *env = opaque;
int cur_level;
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: env %p pin %d level %d\n", __func__,
LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
env, pin, level);
}
#endif
cur_level = (env->irq_input_state >> pin) & 1;
/* Don't generate spurious events */
if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) {
switch (pin) {
case PPC40x_INPUT_RESET_SYS:
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the PowerPC system\n",
LOG_IRQ("%s: reset the PowerPC system\n",
__func__);
}
#endif
ppc40x_system_reset(env);
}
break;
case PPC40x_INPUT_RESET_CHIP:
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the PowerPC chip\n", __func__);
}
#endif
LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
ppc40x_chip_reset(env);
}
break;
case PPC40x_INPUT_RESET_CORE:
/* XXX: TODO: update DBSR[MRR] */
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: reset the PowerPC core\n", __func__);
}
#endif
LOG_IRQ("%s: reset the PowerPC core\n", __func__);
ppc40x_core_reset(env);
}
break;
case PPC40x_INPUT_CINT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the critical IRQ state to %d\n",
LOG_IRQ("%s: set the critical IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
break;
case PPC40x_INPUT_INT:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the external IRQ state to %d\n",
LOG_IRQ("%s: set the external IRQ state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
break;
case PPC40x_INPUT_HALT:
/* Level sensitive - active low */
if (level) {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: stop the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: stop the CPU\n", __func__);
env->halted = 1;
} else {
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: restart the CPU\n", __func__);
}
#endif
LOG_IRQ("%s: restart the CPU\n", __func__);
env->halted = 0;
}
break;
case PPC40x_INPUT_DEBUG:
/* Level sensitive - active high */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: set the debug pin state to %d\n",
LOG_IRQ("%s: set the debug pin state to %d\n",
__func__, level);
}
#endif
ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
break;
default:
/* Unknown pin - do nothing */
#if defined(PPC_DEBUG_IRQ)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: unknown IRQ pin %d\n", __func__, pin);
}
#endif
LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
return;
}
if (level)
@ -453,11 +352,7 @@ uint32_t cpu_ppc_load_tbl (CPUState *env)
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb & 0xFFFFFFFF;
}
@ -468,11 +363,7 @@ static always_inline uint32_t _cpu_ppc_load_tbu (CPUState *env)
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->tb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32;
}
@ -487,12 +378,8 @@ static always_inline void cpu_ppc_store_tb (ppc_tb_t *tb_env, uint64_t vmclk,
uint64_t value)
{
*tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, ticks_per_sec);
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n",
__func__, value, *tb_offsetp);
}
#endif
}
void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
@ -528,11 +415,7 @@ uint32_t cpu_ppc_load_atbl (CPUState *env)
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb & 0xFFFFFFFF;
}
@ -543,11 +426,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env)
uint64_t tb;
tb = cpu_ppc_get_tb(tb_env, qemu_get_clock(vm_clock), tb_env->atb_offset);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
fprintf(logfile, "%s: tb %016" PRIx64 "\n", __func__, tb);
}
#endif
LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb);
return tb >> 32;
}
@ -629,11 +508,7 @@ static always_inline uint32_t _cpu_ppc_load_decr (CPUState *env,
decr = muldiv64(diff, tb_env->decr_freq, ticks_per_sec);
else
decr = -muldiv64(-diff, tb_env->decr_freq, ticks_per_sec);
#if defined(PPC_DEBUG_TB)
if (loglevel != 0) {
fprintf(logfile, "%s: %08" PRIx32 "\n", __func__, decr);
}
#endif
LOG_TB("%s: %08" PRIx32 "\n", __func__, decr);
return decr;
}
@ -668,22 +543,14 @@ uint64_t cpu_ppc_load_purr (CPUState *env)
static always_inline void cpu_ppc_decr_excp (CPUState *env)
{
/* Raise it */
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "raise decrementer exception\n");
}
#endif
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
}
static always_inline void cpu_ppc_hdecr_excp (CPUState *env)
{
/* Raise it */
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "raise decrementer exception\n");
}
#endif
LOG_TB("raise decrementer exception\n");
ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
}
@ -696,12 +563,8 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,
ppc_tb_t *tb_env = env->tb_env;
uint64_t now, next;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__,
decr, value);
}
#endif
now = qemu_get_clock(vm_clock);
next = now + muldiv64(value, ticks_per_sec, tb_env->decr_freq);
if (is_excp)
@ -882,13 +745,9 @@ static void cpu_4xx_fit_cb (void *opaque)
env->spr[SPR_40x_TSR] |= 1 << 26;
if ((env->spr[SPR_40x_TCR] >> 23) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
LOG_TB("%s: ir %d TCR " ADDRX " TSR " ADDRX "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 23) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
#endif
}
/* Programmable interval timer */
@ -902,19 +761,11 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)
!((env->spr[SPR_40x_TCR] >> 26) & 0x1) ||
(is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) {
/* Stop PIT */
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: stop PIT\n", __func__);
}
#endif
LOG_TB("%s: stop PIT\n", __func__);
qemu_del_timer(tb_env->decr_timer);
} else {
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: start PIT %016" PRIx64 "\n",
LOG_TB("%s: start PIT %016" PRIx64 "\n",
__func__, ppcemb_timer->pit_reload);
}
#endif
now = qemu_get_clock(vm_clock);
next = now + muldiv64(ppcemb_timer->pit_reload,
ticks_per_sec, tb_env->decr_freq);
@ -940,16 +791,12 @@ static void cpu_4xx_pit_cb (void *opaque)
if ((env->spr[SPR_40x_TCR] >> 26) & 0x1)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 1);
start_stop_pit(env, tb_env, 1);
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
LOG_TB("%s: ar %d ir %d TCR " ADDRX " TSR " ADDRX " "
"%016" PRIx64 "\n", __func__,
(int)((env->spr[SPR_40x_TCR] >> 22) & 0x1),
(int)((env->spr[SPR_40x_TCR] >> 26) & 0x1),
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR],
ppcemb_timer->pit_reload);
}
#endif
}
/* Watchdog timer */
@ -984,12 +831,8 @@ static void cpu_4xx_wdt_cb (void *opaque)
next = now + muldiv64(next, ticks_per_sec, tb_env->decr_freq);
if (next == now)
next++;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
LOG_TB("%s: TCR " ADDRX " TSR " ADDRX "\n", __func__,
env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]);
}
#endif
switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) {
case 0x0:
case 0x1:
@ -1031,11 +874,7 @@ void store_40x_pit (CPUState *env, target_ulong val)
tb_env = env->tb_env;
ppcemb_timer = tb_env->opaque;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s val" ADDRX "\n", __func__, val);
}
#endif
LOG_TB("%s val" ADDRX "\n", __func__, val);
ppcemb_timer->pit_reload = val;
start_stop_pit(env, tb_env, 0);
}
@ -1047,11 +886,7 @@ target_ulong load_40x_pit (CPUState *env)
void store_booke_tsr (CPUState *env, target_ulong val)
{
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
}
#endif
LOG_TB("%s: val " ADDRX "\n", __func__, val);
env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
if (val & 0x80000000)
ppc_set_irq(env, PPC_INTERRUPT_PIT, 0);
@ -1062,11 +897,7 @@ void store_booke_tcr (CPUState *env, target_ulong val)
ppc_tb_t *tb_env;
tb_env = env->tb_env;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s: val " ADDRX "\n", __func__, val);
}
#endif
LOG_TB("%s: val " ADDRX "\n", __func__, val);
env->spr[SPR_40x_TCR] = val & 0xFFC00000;
start_stop_pit(env, tb_env, 1);
cpu_4xx_wdt_cb(env);
@ -1077,12 +908,8 @@ static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq)
CPUState *env = opaque;
ppc_tb_t *tb_env = env->tb_env;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s set new frequency to %" PRIu32 "\n", __func__,
LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
freq);
}
#endif
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
/* XXX: we should also update all timers */
@ -1102,11 +929,7 @@ clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq)
tb_env->tb_freq = freq;
tb_env->decr_freq = freq;
tb_env->opaque = ppcemb_timer;
#ifdef PPC_DEBUG_TB
if (loglevel != 0) {
fprintf(logfile, "%s freq %" PRIu32 "\n", __func__, freq);
}
#endif
LOG_TB("%s freq %" PRIu32 "\n", __func__, freq);
if (ppcemb_timer != NULL) {
/* We use decr timer for PIT */
tb_env->decr_timer = qemu_new_timer(vm_clock, &cpu_4xx_pit_cb, env);

58
hw/ppc4xx_devs.c
View File

@ -31,6 +31,16 @@
//#define DEBUG_UNASSIGNED
#define DEBUG_UIC
#ifdef DEBUG_UIC
# define LOG_UIC(...) do { \
if (loglevel & CPU_LOG_INT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_UIC(...) do { } while (0)
#endif
/*****************************************************************************/
/* Generic PowerPC 4xx processor instanciation */
CPUState *ppc4xx_init (const char *cpu_model,
@ -294,28 +304,16 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
/* Trigger interrupt if any is pending */
ir = uic->uicsr & uic->uicer & (~uic->uiccr);
cr = uic->uicsr & uic->uicer & uic->uiccr;
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: uicsr %08" PRIx32 " uicer %08" PRIx32
LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32
" uiccr %08" PRIx32 "\n"
" %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n",
__func__, uic->uicsr, uic->uicer, uic->uiccr,
uic->uicsr & uic->uicer, ir, cr);
}
#endif
if (ir != 0x0000000) {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise UIC interrupt\n");
}
#endif
LOG_UIC("Raise UIC interrupt\n");
qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);
} else {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Lower UIC interrupt\n");
}
#endif
LOG_UIC("Lower UIC interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);
}
/* Trigger critical interrupt if any is pending and update vector */
@ -340,18 +338,10 @@ static void ppcuic_trigger_irq (ppcuic_t *uic)
}
}
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Raise UIC critical interrupt - "
LOG_UIC("Raise UIC critical interrupt - "
"vector %08" PRIx32 "\n", uic->uicvr);
}
#endif
} else {
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "Lower UIC critical interrupt\n");
}
#endif
LOG_UIC("Lower UIC critical interrupt\n");
qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);
uic->uicvr = 0x00000000;
}
@ -364,14 +354,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic = opaque;
mask = 1 << (31-irq_num);
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: irq %d level %d uicsr %08" PRIx32
LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32
" mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n",
__func__, irq_num, level,
uic->uicsr, mask, uic->uicsr & mask, level << irq_num);
}
#endif
if (irq_num < 0 || irq_num > 31)
return;
sr = uic->uicsr;
@ -391,12 +377,8 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
uic->level &= ~mask;
}
}
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: irq %d level %d sr %" PRIx32 " => "
LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => "
"%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr);
}
#endif
if (sr != uic->uicsr)
ppcuic_trigger_irq(uic);
}
@ -453,11 +435,7 @@ static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
uic = opaque;
dcrn -= uic->dcr_base;
#ifdef DEBUG_UIC
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
}
#endif
LOG_UIC("%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;

77
kqemu.c
View File

@ -47,6 +47,22 @@
#define DEBUG
//#define PROFILE
#ifdef DEBUG
# define LOG_INT(...) do { \
if (loglevel & CPU_LOG_INT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
# define LOG_INT_STATE(env) \
do { \
if (loglevel & CPU_LOG_INT) \
cpu_dump_state(env, logfile, fprintf, 0); \
} while (0)
#else
# define LOG_INT(...) do { } while (0)
# define LOG_INT_STATE(env) do { } while (0)
#endif
#include <unistd.h>
#include <fcntl.h>
#include "kqemu.h"
@ -241,11 +257,7 @@ int kqemu_init(CPUState *env)
void kqemu_flush_page(CPUState *env, target_ulong addr)
{
#if defined(DEBUG)
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
}
#endif
LOG_INT("kqemu_flush_page: addr=" TARGET_FMT_lx "\n", addr);
if (nb_pages_to_flush >= KQEMU_MAX_PAGES_TO_FLUSH)
nb_pages_to_flush = KQEMU_FLUSH_ALL;
else
@ -254,22 +266,14 @@ void kqemu_flush_page(CPUState *env, target_ulong addr)
void kqemu_flush(CPUState *env, int global)
{
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_flush:\n");
}
#endif
LOG_INT("kqemu_flush:\n");
nb_pages_to_flush = KQEMU_FLUSH_ALL;
}
void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr)
{
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu_set_notdirty: addr=%08lx\n",
LOG_INT("kqemu_set_notdirty: addr=%08lx\n",
(unsigned long)ram_addr);
}
#endif
/* we only track transitions to dirty state */
if (phys_ram_dirty[ram_addr >> TARGET_PAGE_BITS] != 0xff)
return;
@ -703,12 +707,8 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
ti = profile_getclock();
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: cpu_exec: enter\n");
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT("kqemu: cpu_exec: enter\n");
LOG_INT_STATE(env);
for(i = 0; i < CPU_NB_REGS; i++)
kenv->regs[i] = env->regs[i];
kenv->eip = env->eip;
@ -867,11 +867,7 @@ int kqemu_cpu_exec(CPUState *env)
else
env->hflags &= ~HF_OSFXSR_MASK;
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
}
#endif
LOG_INT("kqemu: kqemu_cpu_exec: ret=0x%x\n", ret);
if (ret == KQEMU_RET_SYSCALL) {
/* syscall instruction */
return do_syscall(env, kenv);
@ -884,13 +880,8 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
kqemu_ret_int_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: interrupt v=%02x:\n",
env->exception_index);
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT("kqemu: interrupt v=%02x:\n", env->exception_index);
LOG_INT_STATE(env);
return 1;
} else if ((ret & 0xff00) == KQEMU_RET_EXCEPTION) {
env->exception_index = ret & 0xff;
@ -900,23 +891,15 @@ int kqemu_cpu_exec(CPUState *env)
#ifdef CONFIG_PROFILER
kqemu_ret_excp_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
fprintf(logfile, "kqemu: exception v=%02x e=%04x:\n",
LOG_INT("kqemu: exception v=%02x e=%04x:\n",
env->exception_index, env->error_code);
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 1;
} else if (ret == KQEMU_RET_INTR) {
#ifdef CONFIG_PROFILER
kqemu_ret_intr_count++;
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 0;
} else if (ret == KQEMU_RET_SOFTMMU) {
#ifdef CONFIG_PROFILER
@ -925,11 +908,7 @@ int kqemu_cpu_exec(CPUState *env)
kqemu_record_pc(pc);
}
#endif
#ifdef DEBUG
if (loglevel & CPU_LOG_INT) {
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
LOG_INT_STATE(env);
return 2;
} else {
cpu_dump_state(env, stderr, fprintf, 0);

39
linux-user/vm86.c
View File

@ -29,6 +29,13 @@
//#define DEBUG_VM86
#ifdef DEBUG_VM86
# define LOG_VM86(...) fprintf(logfile, ## __VA_ARGS__);
#else
# define LOG_VM86(...) do { } while (0)
#endif
#define set_flags(X,new,mask) \
((X) = ((X) & ~(mask)) | ((new) & (mask)))
@ -92,10 +99,8 @@ void save_v86_state(CPUX86State *env)
set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
target_v86->regs.eflags = tswap32(env->eflags);
unlock_user_struct(target_v86, ts->target_v86, 1);
#ifdef DEBUG_VM86
fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
env->eflags, env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
env->eflags, env->segs[R_CS].selector, env->eip);
/* restore 32 bit registers */
env->regs[R_EAX] = ts->vm86_saved_regs.eax;
@ -121,9 +126,7 @@ void save_v86_state(CPUX86State *env)
'retval' */
static inline void return_to_32bit(CPUX86State *env, int retval)
{
#ifdef DEBUG_VM86
fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
#endif
LOG_VM86("return_to_32bit: ret=0x%x\n", retval);
save_v86_state(env);
env->regs[R_EAX] = retval;
}
@ -216,10 +219,8 @@ static void do_int(CPUX86State *env, int intno)
segoffs = ldl(int_addr);
if ((segoffs >> 16) == TARGET_BIOSSEG)
goto cannot_handle;
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
intno, segoffs >> 16, segoffs & 0xffff);
#endif
LOG_VM86("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
intno, segoffs >> 16, segoffs & 0xffff);
/* save old state */
ssp = env->segs[R_SS].selector << 4;
sp = env->regs[R_ESP] & 0xffff;
@ -235,9 +236,7 @@ static void do_int(CPUX86State *env, int intno)
clear_AC(env);
return;
cannot_handle:
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
#endif
LOG_VM86("VM86: return to 32 bits int 0x%x\n", intno);
return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
}
@ -274,10 +273,8 @@ void handle_vm86_fault(CPUX86State *env)
ssp = env->segs[R_SS].selector << 4;
sp = env->regs[R_ESP] & 0xffff;
#if defined(DEBUG_VM86)
fprintf(logfile, "VM86 exception %04x:%08x\n",
env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("VM86 exception %04x:%08x\n",
env->segs[R_CS].selector, env->eip);
data32 = 0;
pref_done = 0;
@ -478,10 +475,8 @@ int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
target_v86->vm86plus.vm86dbg_intxxtab, 32);
unlock_user_struct(target_v86, vm86_addr, 0);
#ifdef DEBUG_VM86
fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n",
env->segs[R_CS].selector, env->eip);
#endif
LOG_VM86("do_vm86: cs:ip=%04x:%04x\n",
env->segs[R_CS].selector, env->eip);
/* now the virtual CPU is ready for vm86 execution ! */
out:
return ret;

28
target-alpha/translate.c
View File

@ -37,6 +37,16 @@
#define ALPHA_DEBUG_DISAS
/* #define DO_TB_FLUSH */
#ifdef ALPHA_DEBUG_DISAS
# define LOG_DISAS(...) do { \
if (logfile) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_DISAS(...) do { } while (0)
#endif
typedef struct DisasContext DisasContext;
struct DisasContext {
uint64_t pc;
@ -671,12 +681,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
fn7 = (insn >> 5) & 0x0000007F;
fn2 = (insn >> 5) & 0x00000003;
ret = 0;
#if defined ALPHA_DEBUG_DISAS
if (logfile != NULL) {
fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
opc, ra, rb, rc, disp16);
}
#endif
LOG_DISAS("opc %02x ra %d rb %d rc %d disp16 %04x\n",
opc, ra, rb, rc, disp16);
switch (opc) {
case 0x00:
/* CALL_PAL */
@ -2386,17 +2392,13 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
gen_io_start();
#if defined ALPHA_DEBUG_DISAS
insn_count++;
if (logfile != NULL) {
fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
ctx.pc, ctx.mem_idx);
}
LOG_DISAS("pc " TARGET_FMT_lx " mem_idx %d\n",
ctx.pc, ctx.mem_idx);
#endif
insn = ldl_code(ctx.pc);
#if defined ALPHA_DEBUG_DISAS
insn_count++;
if (logfile != NULL) {
fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
}
LOG_DISAS("opcode %08x %d\n", insn, insn_count);
#endif
num_insns++;
ctx.pc += 4;

26
target-cris/helper.c
View File

@ -28,7 +28,17 @@
#include "exec-all.h"
#include "host-utils.h"
//#define CRIS_HELPER_DEBUG
#ifdef CRIS_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
#if defined(CONFIG_USER_ONLY)
@ -98,10 +108,10 @@ int cpu_cris_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
r = tlb_set_page(env, address, phy, prot, mmu_idx, is_softmmu);
}
if (r > 0)
D(fprintf(logfile, "%s returns %d irqreq=%x addr=%x"
D_LOG("%s returns %d irqreq=%x addr=%x"
" phy=%x ismmu=%d vec=%x pc=%x\n",
__func__, r, env->interrupt_request,
address, res.phy, is_softmmu, res.bf_vec, env->pc));
address, res.phy, is_softmmu, res.bf_vec, env->pc);
return r;
}
@ -109,9 +119,9 @@ void do_interrupt(CPUState *env)
{
int ex_vec = -1;
D(fprintf (logfile, "exception index=%d interrupt_req=%d\n",
D_LOG( "exception index=%d interrupt_req=%d\n",
env->exception_index,
env->interrupt_request));
env->interrupt_request);
switch (env->exception_index)
{
@ -147,13 +157,13 @@ void do_interrupt(CPUState *env)
env->pregs[PR_EXS] = (ex_vec & 0xff) << 8;
if (env->dslot) {
D(fprintf(logfile, "excp isr=%x PC=%x ds=%d SP=%x"
D_LOG("excp isr=%x PC=%x ds=%d SP=%x"
" ERP=%x pid=%x ccs=%x cc=%d %x\n",
ex_vec, env->pc, env->dslot,
env->regs[R_SP],
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->cc_op, env->cc_mask));
env->cc_op, env->cc_mask);
/* We loose the btarget, btaken state here so rexec the
branch. */
env->pregs[PR_ERP] -= env->dslot;
@ -171,11 +181,11 @@ void do_interrupt(CPUState *env)
/* Apply the CRIS CCS shift. Clears U if set. */
cris_shift_ccs(env);
D(fprintf (logfile, "%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
env->pregs[PR_CCS],
env->pregs[PR_PID],
env->pregs[PR_ERP]));
env->pregs[PR_ERP]);
}
target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)

12
target-cris/mmu.c
View File

@ -32,8 +32,10 @@
#ifdef DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
void cris_mmu_init(CPUState *env)
@ -180,9 +182,8 @@ static int cris_mmu_translate_page(struct cris_mmu_result_t *res,
tlb_pid = EXTRACT_FIELD(hi, 0, 7);
tlb_g = EXTRACT_FIELD(lo, 4, 4);
D(fprintf(logfile,
"TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
mmu, set, idx, tlb_vpn, vpage, lo, hi));
D_LOG("TLB[%d][%d][%d] v=%x vpage=%x lo=%x hi=%x\n",
mmu, set, idx, tlb_vpn, vpage, lo, hi);
if ((tlb_g || (tlb_pid == pid))
&& tlb_vpn == vpage) {
match = 1;
@ -314,9 +315,8 @@ void cris_mmu_flush_pid(CPUState *env, uint32_t pid)
if (tlb_v && !tlb_g && (tlb_pid == pid)) {
vaddr = tlb_vpn << TARGET_PAGE_BITS;
D(fprintf(logfile,
"flush pid=%x vaddr=%x\n",
pid, vaddr));
D_LOG("flush pid=%x vaddr=%x\n",
pid, vaddr);
tlb_flush_page(env, vaddr);
}
}

26
target-cris/op_helper.c
View File

@ -25,7 +25,16 @@
#include "helper.h"
#include "host-utils.h"
//#define CRIS_OP_HELPER_DEBUG
#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) fprintf(logfile, ## __VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif
#if !defined(CONFIG_USER_ONLY)
@ -59,8 +68,8 @@ void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
saved_env = env;
env = cpu_single_env;
D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr));
D_LOG("%s pc=%x tpc=%x ra=%x\n", __func__,
env->pc, env->debug1, retaddr);
ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
if (unlikely(ret)) {
if (retaddr) {
@ -155,9 +164,8 @@ void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
env->tlbsets[srs - 1][set][idx].lo = lo;
env->tlbsets[srs - 1][set][idx].hi = hi;
D(fprintf(logfile,
"tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc));
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
tlb_flush_page(env, vaddr);
}
}
@ -213,10 +221,10 @@ void helper_rfe(void)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->btarget));
env->btarget);
cris_ccs_rshift(env);
@ -229,10 +237,10 @@ void helper_rfn(void)
{
int rflag = env->pregs[PR_CCS] & R_FLAG;
D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
env->pregs[PR_ERP], env->pregs[PR_PID],
env->pregs[PR_CCS],
env->btarget));
env->btarget);
cris_ccs_rshift(env);

289
target-cris/translate.c
View File

@ -44,9 +44,12 @@
#define DISAS_CRIS 0
#if DISAS_CRIS
#define DIS(x) if (loglevel & CPU_LOG_TB_IN_ASM) x
# define LOG_DIS(...) do { \
if (loglevel & CPU_LOG_TB_IN_ASM) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
#define DIS(x)
# define LOG_DIS(...) do { } while (0)
#endif
#define D(x)
@ -1344,7 +1347,7 @@ static unsigned int dec_bccq(DisasContext *dc)
tmp = offset;
offset = sign_extend(offset, 8);
DIS(fprintf (logfile, "b%s %x\n", cc_name(cond), dc->pc + offset));
LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
/* op2 holds the condition-code. */
cris_cc_mask(dc, 0);
@ -1358,7 +1361,7 @@ static unsigned int dec_addoq(DisasContext *dc)
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
imm = sign_extend(dc->op1, 7);
DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
cris_cc_mask(dc, 0);
/* Fetch register operand, */
tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
@ -1367,7 +1370,7 @@ static unsigned int dec_addoq(DisasContext *dc)
}
static unsigned int dec_addq(DisasContext *dc)
{
DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
@ -1383,7 +1386,7 @@ static unsigned int dec_moveq(DisasContext *dc)
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
return 2;
@ -1392,7 +1395,7 @@ static unsigned int dec_subq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_SUB,
@ -1405,7 +1408,7 @@ static unsigned int dec_cmpq(DisasContext *dc)
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu(dc, CC_OP_CMP,
@ -1418,7 +1421,7 @@ static unsigned int dec_andq(DisasContext *dc)
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_AND,
@ -1430,7 +1433,7 @@ static unsigned int dec_orq(DisasContext *dc)
uint32_t imm;
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
imm = sign_extend(dc->op1, 5);
DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_OR,
@ -1440,7 +1443,7 @@ static unsigned int dec_orq(DisasContext *dc)
static unsigned int dec_btstq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
@ -1455,7 +1458,7 @@ static unsigned int dec_btstq(DisasContext *dc)
static unsigned int dec_asrq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
@ -1467,7 +1470,7 @@ static unsigned int dec_asrq(DisasContext *dc)
static unsigned int dec_lslq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
@ -1481,7 +1484,7 @@ static unsigned int dec_lslq(DisasContext *dc)
static unsigned int dec_lsrq(DisasContext *dc)
{
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
@ -1496,8 +1499,8 @@ static unsigned int dec_move_r(DisasContext *dc)
{
int size = memsize_zz(dc);
DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("move.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
if (size == 4) {
@ -1524,8 +1527,8 @@ static unsigned int dec_scc_r(DisasContext *dc)
{
int cond = dc->op2;
DIS(fprintf (logfile, "s%s $r%u\n",
cc_name(cond), dc->op1));
LOG_DIS("s%s $r%u\n",
cc_name(cond), dc->op1);
if (cond != CC_A)
{
@ -1568,8 +1571,8 @@ static unsigned int dec_and_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("and.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
@ -1583,8 +1586,8 @@ static unsigned int dec_and_r(DisasContext *dc)
static unsigned int dec_lz_r(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "lz $r%u, $r%u\n",
dc->op1, dc->op2));
LOG_DIS("lz $r%u, $r%u\n",
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
@ -1598,8 +1601,8 @@ static unsigned int dec_lsl_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("lsl.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
@ -1615,8 +1618,8 @@ static unsigned int dec_lsr_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("lsr.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
@ -1632,8 +1635,8 @@ static unsigned int dec_asr_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("asr.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
@ -1649,8 +1652,8 @@ static unsigned int dec_muls_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("muls.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZV);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
@ -1665,8 +1668,8 @@ static unsigned int dec_mulu_r(DisasContext *dc)
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("mulu.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZV);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1679,7 +1682,7 @@ static unsigned int dec_mulu_r(DisasContext *dc)
static unsigned int dec_dstep_r(DisasContext *dc)
{
DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu(dc, CC_OP_DSTEP,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
@ -1690,8 +1693,8 @@ static unsigned int dec_xor_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("xor.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
BUG_ON(size != 4); /* xor is dword. */
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
@ -1706,8 +1709,8 @@ static unsigned int dec_bound_r(DisasContext *dc)
{
TCGv l0;
int size = memsize_zz(dc);
DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("bound.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
l0 = tcg_temp_local_new();
dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
@ -1720,8 +1723,8 @@ static unsigned int dec_cmp_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("cmp.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1735,8 +1738,8 @@ static unsigned int dec_abs_r(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "abs $r%u, $r%u\n",
dc->op1, dc->op2));
LOG_DIS("abs $r%u, $r%u\n",
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
@ -1754,8 +1757,8 @@ static unsigned int dec_add_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("add.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1767,8 +1770,8 @@ static unsigned int dec_add_r(DisasContext *dc)
static unsigned int dec_addc_r(DisasContext *dc)
{
DIS(fprintf (logfile, "addc $r%u, $r%u\n",
dc->op1, dc->op2));
LOG_DIS("addc $r%u, $r%u\n",
dc->op1, dc->op2);
cris_evaluate_flags(dc);
/* Set for this insn. */
dc->flagx_known = 1;
@ -1782,8 +1785,8 @@ static unsigned int dec_addc_r(DisasContext *dc)
static unsigned int dec_mcp_r(DisasContext *dc)
{
DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
dc->op2, dc->op1));
LOG_DIS("mcp $p%u, $r%u\n",
dc->op2, dc->op1);
cris_evaluate_flags(dc);
cris_cc_mask(dc, CC_MASK_RNZV);
cris_alu(dc, CC_OP_MCP,
@ -1813,8 +1816,8 @@ static unsigned int dec_swap_r(DisasContext *dc)
#if DISAS_CRIS
char modename[4];
#endif
DIS(fprintf (logfile, "swap%s $r%u\n",
swapmode_name(dc->op2, modename), dc->op1));
LOG_DIS("swap%s $r%u\n",
swapmode_name(dc->op2, modename), dc->op1);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
@ -1837,8 +1840,8 @@ static unsigned int dec_or_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("or.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1850,8 +1853,8 @@ static unsigned int dec_or_r(DisasContext *dc)
static unsigned int dec_addi_r(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
LOG_DIS("addi.%c $r%u, $r%u\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
cris_cc_mask(dc, 0);
t0 = tcg_temp_new();
tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
@ -1863,8 +1866,8 @@ static unsigned int dec_addi_r(DisasContext *dc)
static unsigned int dec_addi_acr(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
cris_cc_mask(dc, 0);
t0 = tcg_temp_new();
tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
@ -1877,8 +1880,8 @@ static unsigned int dec_neg_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("neg.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1890,8 +1893,8 @@ static unsigned int dec_neg_r(DisasContext *dc)
static unsigned int dec_btst_r(DisasContext *dc)
{
DIS(fprintf (logfile, "btst $r%u, $r%u\n",
dc->op1, dc->op2));
LOG_DIS("btst $r%u, $r%u\n",
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
cris_evaluate_flags(dc);
gen_helper_btst(cpu_PR[PR_CCS], cpu_R[dc->op2],
@ -1907,8 +1910,8 @@ static unsigned int dec_sub_r(DisasContext *dc)
{
TCGv t[2];
int size = memsize_zz(dc);
DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2));
LOG_DIS("sub.%c $r%u, $r%u\n",
memsize_char(size), dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
cris_alu_alloc_temps(dc, size, t);
dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
@ -1922,9 +1925,9 @@ static unsigned int dec_movu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
LOG_DIS("movu.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
@ -1939,9 +1942,9 @@ static unsigned int dec_movs_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
LOG_DIS("movs.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new();
@ -1958,9 +1961,9 @@ static unsigned int dec_addu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
LOG_DIS("addu.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
@ -1977,9 +1980,9 @@ static unsigned int dec_adds_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
LOG_DIS("adds.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
@ -1996,9 +1999,9 @@ static unsigned int dec_subu_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
LOG_DIS("subu.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
@ -2015,9 +2018,9 @@ static unsigned int dec_subs_r(DisasContext *dc)
{
TCGv t0;
int size = memsize_z(dc);
DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
LOG_DIS("subs.%c $r%u, $r%u\n",
memsize_char(size),
dc->op1, dc->op2));
dc->op1, dc->op2);
cris_cc_mask(dc, CC_MASK_NZVC);
t0 = tcg_temp_new();
@ -2038,15 +2041,15 @@ static unsigned int dec_setclrf(DisasContext *dc)
flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
| EXTRACT_FIELD(dc->ir, 0, 3);
if (set && flags == 0) {
DIS(fprintf (logfile, "nop\n"));
LOG_DIS("nop\n");
return 2;
} else if (!set && (flags & 0x20)) {
DIS(fprintf (logfile, "di\n"));
LOG_DIS("di\n");
}
else {
DIS(fprintf (logfile, "%sf %x\n",
LOG_DIS("%sf %x\n",
set ? "set" : "clr",
flags));
flags);
}
/* User space is not allowed to touch these. Silently ignore. */
@ -2101,14 +2104,14 @@ static unsigned int dec_setclrf(DisasContext *dc)
static unsigned int dec_move_rs(DisasContext *dc)
{
DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
gen_helper_movl_sreg_reg(tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
return 2;
}
static unsigned int dec_move_sr(DisasContext *dc)
{
DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
cris_cc_mask(dc, 0);
gen_helper_movl_reg_sreg(tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
return 2;
@ -2117,7 +2120,7 @@ static unsigned int dec_move_sr(DisasContext *dc)
static unsigned int dec_move_rp(DisasContext *dc)
{
TCGv t[2];
DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
t[0] = tcg_temp_new();
@ -2147,7 +2150,7 @@ static unsigned int dec_move_rp(DisasContext *dc)
static unsigned int dec_move_pr(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
LOG_DIS("move $p%u, $r%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
if (dc->op2 == PR_CCS)
@ -2165,10 +2168,10 @@ static unsigned int dec_move_mr(DisasContext *dc)
{
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
LOG_DIS("move.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
if (memsize == 4) {
insn_len = dec_prep_move_m(dc, 0, 4, cpu_R[dc->op2]);
@ -2208,10 +2211,10 @@ static unsigned int dec_movs_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
LOG_DIS("movs.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
@ -2229,10 +2232,10 @@ static unsigned int dec_addu_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
LOG_DIS("addu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
@ -2250,10 +2253,10 @@ static unsigned int dec_adds_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
LOG_DIS("adds.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
@ -2270,10 +2273,10 @@ static unsigned int dec_subu_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
LOG_DIS("subu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
@ -2290,10 +2293,10 @@ static unsigned int dec_subs_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
LOG_DIS("subs.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
/* sign extend. */
@ -2311,10 +2314,10 @@ static unsigned int dec_movu_m(DisasContext *dc)
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
LOG_DIS("movu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2330,10 +2333,10 @@ static unsigned int dec_cmpu_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2349,10 +2352,10 @@ static unsigned int dec_cmps_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_z(dc);
int insn_len;
DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
@ -2370,10 +2373,10 @@ static unsigned int dec_cmp_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2391,10 +2394,10 @@ static unsigned int dec_test_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
LOG_DIS("test.%d [$r%u%s] op2=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_evaluate_flags(dc);
@ -2415,10 +2418,10 @@ static unsigned int dec_and_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
LOG_DIS("and.%d [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2434,10 +2437,10 @@ static unsigned int dec_add_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
LOG_DIS("add.%d [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2454,10 +2457,10 @@ static unsigned int dec_addo_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
LOG_DIS("add.%d [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 1, memsize, t[0], t[1]);
@ -2473,10 +2476,10 @@ static unsigned int dec_bound_m(DisasContext *dc)
TCGv l[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
LOG_DIS("bound.%d [$r%u%s, $r%u\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
l[0] = tcg_temp_local_new();
l[1] = tcg_temp_local_new();
@ -2493,9 +2496,9 @@ static unsigned int dec_addc_mr(DisasContext *dc)
{
TCGv t[2];
int insn_len = 2;
DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
LOG_DIS("addc [$r%u%s, $r%u\n",
dc->op1, dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_evaluate_flags(dc);
@ -2517,10 +2520,10 @@ static unsigned int dec_sub_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2, dc->ir, dc->zzsize));
dc->op2, dc->ir, dc->zzsize);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2536,10 +2539,10 @@ static unsigned int dec_or_m(DisasContext *dc)
TCGv t[2];
int memsize = memsize_zz(dc);
int insn_len;
DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
LOG_DIS("or.%d [$r%u%s, $r%u pc=%x\n",
memsize_char(memsize),
dc->op1, dc->postinc ? "+]" : "]",
dc->op2, dc->pc));
dc->op2, dc->pc);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2557,11 +2560,11 @@ static unsigned int dec_move_mp(DisasContext *dc)
int memsize = memsize_zz(dc);
int insn_len = 2;
DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
LOG_DIS("move.%c [$r%u%s, $p%u\n",
memsize_char(memsize),
dc->op1,
dc->postinc ? "+]" : "]",
dc->op2));
dc->op2);
cris_alu_m_alloc_temps(t);
insn_len = dec_prep_alu_m(dc, 0, memsize, t[0], t[1]);
@ -2590,9 +2593,9 @@ static unsigned int dec_move_pm(DisasContext *dc)
memsize = preg_sizes[dc->op2];
DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
LOG_DIS("move.%c $p%u, [$r%u%s\n",
memsize_char(memsize),
dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
dc->op2, dc->op1, dc->postinc ? "+]" : "]");
/* prepare store. Address in T0, value in T1. */
if (dc->op2 == PR_CCS)
@ -2617,8 +2620,8 @@ static unsigned int dec_movem_mr(DisasContext *dc)
int i;
int nr = dc->op2 + 1;
DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
dc->postinc ? "+]" : "]", dc->op2));
LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
dc->postinc ? "+]" : "]", dc->op2);
addr = tcg_temp_new();
/* There are probably better ways of doing this. */
@ -2661,8 +2664,8 @@ static unsigned int dec_movem_rm(DisasContext *dc)
TCGv addr;
int i;
DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
dc->postinc ? "+]" : "]"));
LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
dc->postinc ? "+]" : "]");
cris_flush_cc_state(dc);
@ -2690,8 +2693,8 @@ static unsigned int dec_move_rm(DisasContext *dc)
memsize = memsize_zz(dc);
DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
memsize, dc->op2, dc->op1));
LOG_DIS("move.%d $r%u, [$r%u]\n",
memsize, dc->op2, dc->op1);
/* prepare store. */
cris_flush_cc_state(dc);
@ -2705,8 +2708,8 @@ static unsigned int dec_move_rm(DisasContext *dc)
static unsigned int dec_lapcq(DisasContext *dc)
{
DIS(fprintf (logfile, "lapcq %x, $r%u\n",
dc->pc + dc->op1*2, dc->op2));
LOG_DIS("lapcq %x, $r%u\n",
dc->pc + dc->op1*2, dc->op2);
cris_cc_mask(dc, 0);
tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
return 2;
@ -2722,7 +2725,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
cris_cc_mask(dc, 0);
imm = ldl_code(dc->pc + 2);
DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
pc = dc->pc;
pc += imm;
@ -2733,7 +2736,7 @@ static unsigned int dec_lapc_im(DisasContext *dc)
/* Jump to special reg. */
static unsigned int dec_jump_p(DisasContext *dc)
{
DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
LOG_DIS("jump $p%u\n", dc->op2);
if (dc->op2 == PR_CCS)
cris_evaluate_flags(dc);
@ -2748,7 +2751,7 @@ static unsigned int dec_jump_p(DisasContext *dc)
/* Jump and save. */
static unsigned int dec_jas_r(DisasContext *dc)
{
DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
@ -2766,7 +2769,7 @@ static unsigned int dec_jas_im(DisasContext *dc)
imm = ldl_code(dc->pc + 2);
DIS(fprintf (logfile, "jas 0x%x\n", imm));
LOG_DIS("jas 0x%x\n", imm);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
@ -2782,7 +2785,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
imm = ldl_code(dc->pc + 2);
DIS(fprintf (logfile, "jasc 0x%x\n", imm));
LOG_DIS("jasc 0x%x\n", imm);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
@ -2794,7 +2797,7 @@ static unsigned int dec_jasc_im(DisasContext *dc)
static unsigned int dec_jasc_r(DisasContext *dc)
{
DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
@ -2810,9 +2813,9 @@ static unsigned int dec_bcc_im(DisasContext *dc)
offset = ldsw_code(dc->pc + 2);
DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
LOG_DIS("b%s %d pc=%x dst=%x\n",
cc_name(cond), offset,
dc->pc, dc->pc + offset));
dc->pc, dc->pc + offset);
cris_cc_mask(dc, 0);
/* op2 holds the condition-code. */
@ -2827,7 +2830,7 @@ static unsigned int dec_bas_im(DisasContext *dc)
simm = ldl_code(dc->pc + 2);
DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
@ -2842,7 +2845,7 @@ static unsigned int dec_basc_im(DisasContext *dc)
int32_t simm;
simm = ldl_code(dc->pc + 2);
DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
cris_cc_mask(dc, 0);
/* Store the return address in Pd. */
t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
@ -2866,20 +2869,20 @@ static unsigned int dec_rfe_etc(DisasContext *dc)
switch (dc->op2 & 7) {
case 2:
/* rfe. */
DIS(fprintf(logfile, "rfe\n"));
LOG_DIS("rfe\n");
cris_evaluate_flags(dc);
gen_helper_rfe();
dc->is_jmp = DISAS_UPDATE;
break;
case 5:
/* rfn. */
DIS(fprintf(logfile, "rfn\n"));
LOG_DIS("rfn\n");
cris_evaluate_flags(dc);
gen_helper_rfn();
dc->is_jmp = DISAS_UPDATE;
break;
case 6:
DIS(fprintf(logfile, "break %d\n", dc->op1));
LOG_DIS("break %d\n", dc->op1);
cris_evaluate_flags (dc);
/* break. */
tcg_gen_movi_tl(env_pc, dc->pc + 2);
@ -3231,7 +3234,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
}
/* Pretty disas. */
DIS(fprintf(logfile, "%8.8x:\t", dc->pc));
LOG_DIS("%8.8x:\t", dc->pc);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();

57
target-i386/op_helper.c
View File

@ -24,6 +24,22 @@
//#define DEBUG_PCALL
#ifdef DEBUG_PCALL
# define LOG_PCALL(...) do { \
if (loglevel & CPU_LOG_PCALL) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
# define LOG_PCALL_STATE(env) do { \
if (loglevel & CPU_LOG_PCALL) \
cpu_dump_state((env), logfile, fprintf, X86_DUMP_CCOP); \
} while (0)
#else
# define LOG_PCALL(...) do { } while (0)
# define LOG_PCALL_STATE(env) do { } while (0)
#endif
#if 0
#define raise_exception_err(a, b)\
do {\
@ -277,10 +293,7 @@ static void switch_tss(int tss_selector,
target_ulong ptr;
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL)
fprintf(logfile, "switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
#endif
LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type, source);
/* if task gate, we read the TSS segment and we load it */
if (type == 5) {
@ -2276,23 +2289,14 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
target_ulong ssp, old_ssp, next_eip;
next_eip = env->eip + next_eip_addend;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "lcall %04x:%08x s=%d\n",
new_cs, (uint32_t)new_eip, shift);
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
}
#endif
LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
LOG_PCALL_STATE(env);
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, 0);
if (load_segment(&e1, &e2, new_cs) != 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
cpl = env->hflags & HF_CPL_MASK;
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "desc=%08x:%08x\n", e1, e2);
}
#endif
LOG_PCALL("desc=%08x:%08x\n", e1, e2);
if (e2 & DESC_S_MASK) {
if (!(e2 & DESC_CS_MASK))
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
@ -2396,11 +2400,8 @@ void helper_lcall_protected(int new_cs, target_ulong new_eip,
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
/* to inner privilege */
get_ss_esp_from_tss(&ss, &sp, dpl);
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL)
fprintf(logfile, "new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx "\n",
ss, sp, param_count, ESP);
#endif
if ((ss & 0xfffc) == 0)
raise_exception_err(EXCP0A_TSS, ss & 0xfffc);
if ((ss & 3) != dpl)
@ -2587,13 +2588,9 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
if (is_iret)
POPW(ssp, sp, sp_mask, new_eflags);
}
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
new_cs, new_eip, shift, addend);
cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
}
#endif
LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n",
new_cs, new_eip, shift, addend);
LOG_PCALL_STATE(env);
if ((new_cs & 0xfffc) == 0)
raise_exception_err(EXCP0D_GPF, new_cs & 0xfffc);
if (load_segment(&e1, &e2, new_cs) != 0)
@ -2643,12 +2640,8 @@ static inline void helper_ret_protected(int shift, int is_iret, int addend)
POPW(ssp, sp, sp_mask, new_esp);
POPW(ssp, sp, sp_mask, new_ss);
}
#ifdef DEBUG_PCALL
if (loglevel & CPU_LOG_PCALL) {
fprintf(logfile, "new ss:esp=%04x:" TARGET_FMT_lx "\n",
LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n",
new_ss, new_esp);
}
#endif
if ((new_ss & 0xfffc) == 0) {
#ifdef TARGET_X86_64
/* NULL ss is allowed in long mode if cpl != 3*/

114
target-mips/translate.c
View File

@ -521,8 +521,14 @@ do { \
ctx->pc, ctx->opcode , ##args); \
} \
} while (0)
#define LOG_DISAS(...) \
do { \
if (loglevel & CPU_LOG_TB_IN_ASM) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
#define MIPS_DEBUG(fmt, args...) do { } while(0)
#define LOG_DISAS(...) do { } while (0)
#endif
#define MIPS_INVAL(op) \
@ -758,12 +764,7 @@ static inline void gen_save_pc(target_ulong pc)
static inline void save_cpu_state (DisasContext *ctx, int do_save_pc)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "hflags %08x saved %08x\n",
ctx->hflags, ctx->saved_hflags);
}
#endif
LOG_DISAS("hflags %08x saved %08x\n", ctx->hflags, ctx->saved_hflags);
if (do_save_pc && ctx->pc != ctx->saved_pc) {
gen_save_pc(ctx->pc);
ctx->saved_pc = ctx->pc;
@ -2314,11 +2315,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile,
"Branch in delay slot at PC 0x" TARGET_FMT_lx "\n",
ctx->pc);
}
LOG_DISAS("Branch in delay slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc);
#endif
generate_exception(ctx, EXCP_RI);
goto out;
@ -3295,21 +3292,11 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mfc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@ -3899,12 +3886,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
gen_io_end();
@ -3913,12 +3895,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int se
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("mtc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@ -4481,21 +4458,11 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmfc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmfc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
@ -5072,12 +5039,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
gen_io_end();
@ -5086,12 +5048,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, TCGv t0, int reg, int s
return;
die:
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
rn, reg, sel);
}
#endif
LOG_DISAS("dmtc0 %s (reg %d sel %d)\n", rn, reg, sel);
generate_exception(ctx, EXCP_RI);
}
#endif /* TARGET_MIPS64 */
@ -5249,24 +5206,14 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
rt, u, sel, h);
}
#endif
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
gen_store_gpr(t0, rd);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n",
rt, u, sel, h);
}
#endif
LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
@ -5424,23 +5371,13 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
default:
goto die;
}
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
rd, u, sel, h);
}
#endif
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
tcg_temp_free(t0);
return;
die:
tcg_temp_free(t0);
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n",
rd, u, sel, h);
}
#endif
LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h);
generate_exception(ctx, EXCP_RI);
}
@ -8272,11 +8209,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
#ifdef MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "\ntb %p idx %d hflags %04x\n",
tb, ctx.mem_idx, ctx.hflags);
#endif
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_icount_start();
while (ctx.bstate == BS_NONE) {
if (unlikely(!TAILQ_EMPTY(&env->breakpoints))) {
@ -8364,10 +8297,7 @@ done_generating:
tb->icount = num_insns;
}
#ifdef DEBUG_DISAS
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "\n");
#endif
LOG_DISAS("\n");
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
target_disas(logfile, pc_start, ctx.pc - pc_start, 0);

328
target-ppc/helper.c
View File

@ -39,6 +39,58 @@
//#define DEBUG_EXCEPTIONS
//#define FLUSH_ALL_TLBS
#ifdef DEBUG_MMU
# define LOG_MMU(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
# define LOG_MMU_STATE(env) do { \
if (loglevel) \
cpu_dump_state(env, logfile, fprintf, 0); \
} while (0)
#else
# define LOG_MMU(...) do { } while (0)
# define LOG_MMU_STATE(...) do { } while (0)
#endif
#ifdef DEBUG_SOFTWARE_TLB
# define LOG_SWTLB(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
#ifdef DEBUG_BATS
# define LOG_BATS(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_BATS(...) do { } while (0)
#endif
#ifdef DEBUG_SLB
# define LOG_SLB(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_SLB(...) do { } while (0)
#endif
#ifdef DEBUG_EXCEPTIONS
# define LOG_EXCP(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_EXCP(...) do { } while (0)
#endif
/*****************************************************************************/
/* PowerPC MMU emulation */
@ -218,16 +270,10 @@ static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
ret = check_prot(ctx->prot, rw, type);
if (ret == 0) {
/* Access granted */
#if defined (DEBUG_MMU)
if (loglevel != 0)
fprintf(logfile, "PTE access granted !\n");
#endif
LOG_MMU("PTE access granted !\n");
} else {
/* Access right violation */
#if defined (DEBUG_MMU)
if (loglevel != 0)
fprintf(logfile, "PTE access rejected\n");
#endif
LOG_MMU("PTE access rejected\n");
}
}
}
@ -298,11 +344,7 @@ static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
ppc6xx_tlb_t *tlb;
int nr, max;
#if defined (DEBUG_SOFTWARE_TLB) && 0
if (loglevel != 0) {
fprintf(logfile, "Invalidate all TLBs\n");
}
#endif
//LOG_SWTLB("Invalidate all TLBs\n");
/* Invalidate all defined software TLB */
max = env->nb_tlb;
if (env->id_tlbs == 1)
@ -328,12 +370,8 @@ static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);
tlb = &env->tlb[nr].tlb6;
if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",
LOG_SWTLB("TLB invalidate %d/%d " ADDRX "\n",
nr, env->nb_tlb, eaddr);
}
#endif
pte_invalidate(&tlb->pte0);
tlb_flush_page(env, tlb->EPN);
}
@ -359,12 +397,8 @@ void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);
tlb = &env->tlb[nr].tlb6;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
LOG_SWTLB("Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);
}
#endif
/* Invalidate any pending reference in Qemu for this virtual address */
__ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);
tlb->pte0 = pte0;
@ -390,27 +424,19 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
tlb = &env->tlb[nr].tlb6;
/* This test "emulates" the PTE index match for hardware TLBs */
if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX
LOG_SWTLB("TLB %d/%d %s [" ADDRX " " ADDRX
"] <> " ADDRX "\n",
nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);
}
#endif
continue;
}
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
LOG_SWTLB("TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX
" %c %c\n",
nr, env->nb_tlb,
pte_is_valid(tlb->pte0) ? "valid" : "inval",
tlb->EPN, eaddr, tlb->pte1,
rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');
}
#endif
switch (pte32_check(ctx, tlb->pte0, tlb->pte1, 0, rw, access_type)) {
case -3:
/* TLB inconsistency */
@ -437,12 +463,8 @@ static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
}
if (best != -1) {
done:
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "found TLB at addr " PADDRX " prot=%01x ret=%d\n",
LOG_SWTLB("found TLB at addr " PADDRX " prot=%01x ret=%d\n",
ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);
}
#endif
/* Update page flags */
pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);
}
@ -485,12 +507,8 @@ static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
int key, pp, valid, prot;
bl = (*BATl & 0x0000003F) << 17;
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "b %02x ==> bl " ADDRX " msk " ADDRX "\n",
LOG_BATS("b %02x ==> bl " ADDRX " msk " ADDRX "\n",
(uint8_t)(*BATl & 0x0000003F), bl, ~bl);
}
#endif
prot = 0;
valid = (*BATl >> 6) & 1;
if (valid) {
@ -514,12 +532,8 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
int i, valid, prot;
int ret = -1;
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "%s: %cBAT v " ADDRX "\n", __func__,
LOG_BATS("%s: %cBAT v " ADDRX "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', virtual);
}
#endif
switch (type) {
case ACCESS_CODE:
BATlt = env->IBAT[1];
@ -541,13 +555,9 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
} else {
bat_size_prot(env, &bl, &valid, &prot, BATu, BATl);
}
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
LOG_BATS("%s: %cBAT%d v " ADDRX " BATu " ADDRX
" BATl " ADDRX "\n", __func__,
type == ACCESS_CODE ? 'I' : 'D', i, virtual, *BATu, *BATl);
}
#endif
if ((virtual & 0xF0000000) == BEPIu &&
((virtual & 0x0FFE0000) & ~bl) == BEPIl) {
/* BAT matches */
@ -559,28 +569,25 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
/* Compute access rights */
ctx->prot = prot;
ret = check_prot(ctx->prot, rw, type);
#if defined (DEBUG_BATS)
if (ret == 0 && loglevel != 0) {
fprintf(logfile, "BAT %d match: r " PADDRX " prot=%c%c\n",
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
}
#endif
if (ret == 0)
LOG_BATS("BAT %d match: r " PADDRX " prot=%c%c\n",
i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',
ctx->prot & PAGE_WRITE ? 'W' : '-');
break;
}
}
}
if (ret < 0) {
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "no BAT match for " ADDRX ":\n", virtual);
#if defined(DEBUG_BATS)
if (IS_LOGGING) {
QEMU_LOG0("no BAT match for " ADDRX ":\n", virtual);
for (i = 0; i < 4; i++) {
BATu = &BATut[i];
BATl = &BATlt[i];
BEPIu = *BATu & 0xF0000000;
BEPIl = *BATu & 0x0FFE0000;
bl = (*BATu & 0x00001FFC) << 15;
fprintf(logfile, "%s: %cBAT%d v " ADDRX " BATu " ADDRX
QEMU_LOG0("%s: %cBAT%d v " ADDRX " BATu " ADDRX
" BATl " ADDRX " \n\t" ADDRX " " ADDRX " " ADDRX "\n",
__func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,
*BATu, *BATl, BEPIu, BEPIl, bl);
@ -588,7 +595,6 @@ static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
}
#endif
}
/* No hit */
return ret;
}
@ -609,30 +615,22 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
pte0 = ldq_phys(base + (i * 16));
pte1 = ldq_phys(base + (i * 16) + 8);
r = pte64_check(ctx, pte0, pte1, h, rw, type);
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
" %d %d %d " ADDRX "\n",
base + (i * 16), pte0, pte1,
(int)(pte0 & 1), h, (int)((pte0 >> 1) & 1),
ctx->ptem);
}
#endif
} else
#endif
{
pte0 = ldl_phys(base + (i * 8));
pte1 = ldl_phys(base + (i * 8) + 4);
r = pte32_check(ctx, pte0, pte1, h, rw, type);
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "Load pte from " ADDRX " => " ADDRX " " ADDRX
LOG_MMU("Load pte from " ADDRX " => " ADDRX " " ADDRX
" %d %d %d " ADDRX "\n",
base + (i * 8), pte0, pte1,
(int)(pte0 >> 31), h, (int)((pte0 >> 6) & 1),
ctx->ptem);
}
#endif
}
switch (r) {
case -3:
@ -660,12 +658,8 @@ static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
}
if (good != -1) {
done:
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "found PTE at addr " PADDRX " prot=%01x ret=%d\n",
LOG_MMU("found PTE at addr " PADDRX " prot=%01x ret=%d\n",
ctx->raddr, ctx->prot, ret);
}
#endif
/* Update page flags */
pte1 = ctx->raddr;
if (pte_update_flags(ctx, &pte1, ret, rw) == 1) {
@ -729,22 +723,14 @@ static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
ret = -5;
sr_base = env->spr[SPR_ASR];
#if defined(DEBUG_SLB)
if (loglevel != 0) {
fprintf(logfile, "%s: eaddr " ADDRX " base " PADDRX "\n",
LOG_SLB("%s: eaddr " ADDRX " base " PADDRX "\n",
__func__, eaddr, sr_base);
}
#endif
mask = 0x0000000000000000ULL; /* Avoid gcc warning */
for (n = 0; n < env->slb_nr; n++) {
tmp64 = ldq_phys(sr_base);
tmp = ldl_phys(sr_base + 8);
#if defined(DEBUG_SLB)
if (loglevel != 0) {
fprintf(logfile, "%s: seg %d " PADDRX " %016" PRIx64 " %08"
LOG_SLB("%s: seg %d " PADDRX " %016" PRIx64 " %08"
PRIx32 "\n", __func__, n, sr_base, tmp64, tmp);
}
#endif
if (slb_is_valid(tmp64)) {
/* SLB entry is valid */
switch (tmp64 & 0x0000000006000000ULL) {
@ -848,12 +834,8 @@ target_ulong ppc_load_slb (CPUPPCState *env, int slb_nr)
} else {
rt = 0;
}
#if defined(DEBUG_SLB)
if (loglevel != 0) {
fprintf(logfile, "%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
LOG_SLB("%s: " PADDRX " %016" PRIx64 " %08" PRIx32 " => %d "
ADDRX "\n", __func__, sr_base, tmp64, tmp, slb_nr, rt);
}
#endif
return rt;
}
@ -875,13 +857,9 @@ void ppc_store_slb (CPUPPCState *env, int slb_nr, target_ulong rs)
tmp64 |= 1 << 27;
/* Set ESID */
tmp64 |= (uint32_t)slb_nr << 28;
#if defined(DEBUG_SLB)
if (loglevel != 0) {
fprintf(logfile, "%s: %d " ADDRX " => " PADDRX " %016" PRIx64
LOG_SLB("%s: %d " ADDRX " => " PADDRX " %016" PRIx64
" %08" PRIx32 "\n", __func__,
slb_nr, rs, sr_base, tmp64, tmp);
}
#endif
/* Write SLB entry to memory */
stq_phys(sr_base, tmp64);
stl_phys(sr_base + 8, tmp);
@ -911,11 +889,7 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
pr = msr_pr;
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "Check SLBs\n");
}
#endif
LOG_MMU("Check SLBs\n");
ret = slb_lookup(env, eaddr, &vsid, &page_mask, &attr);
if (ret < 0)
return ret;
@ -941,22 +915,14 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
vsid_sh = 6;
sdr_sh = 16;
sdr_mask = 0xFFC0;
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "Check segment v=" ADDRX " %d " ADDRX
LOG_MMU("Check segment v=" ADDRX " %d " ADDRX
" nip=" ADDRX " lr=" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip,
env->lr, (int)msr_ir, (int)msr_dr, pr != 0 ? 1 : 0,
rw, type);
}
#endif
}
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " ADDRX "\n",
ctx->key, ds, ctx->nx, vsid);
}
#endif
ret = -1;
if (!ds) {
/* Check if instruction fetch is allowed, if needed */
@ -977,23 +943,15 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
hash = ((vsid ^ pgidx) << vsid_sh) & vsid_mask;
}
mask = (htab_mask << sdr_sh) | sdr_mask;
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
" mask " PADDRX " " ADDRX "\n",
sdr, sdr_sh, hash, mask, page_mask);
}
#endif
ctx->pg_addr[0] = get_pgaddr(sdr, sdr_sh, hash, mask);
/* Secondary table address */
hash = (~hash) & vsid_mask;
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "sdr " PADDRX " sh %d hash " PADDRX
LOG_MMU("sdr " PADDRX " sh %d hash " PADDRX
" mask " PADDRX "\n",
sdr, sdr_sh, hash, mask);
}
#endif
ctx->pg_addr[1] = get_pgaddr(sdr, sdr_sh, hash, mask);
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) {
@ -1011,26 +969,19 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
/* Software TLB search */
ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);
} else {
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "0 sdr1=" PADDRX " vsid=" ADDRX " "
LOG_MMU("0 sdr1=" PADDRX " vsid=" ADDRX " "
"api=" ADDRX " hash=" PADDRX
" pg_addr=" PADDRX "\n",
sdr, vsid, pgidx, hash, ctx->pg_addr[0]);
}
#endif
/* Primary table lookup */
ret = find_pte(env, ctx, 0, rw, type);
if (ret < 0) {
/* Secondary table lookup */
#if defined (DEBUG_MMU)
if (eaddr != 0xEFFFFFFF && loglevel != 0) {
fprintf(logfile, "1 sdr1=" PADDRX " vsid=" ADDRX " "
if (eaddr != 0xEFFFFFFF)
LOG_MMU("1 sdr1=" PADDRX " vsid=" ADDRX " "
"api=" ADDRX " hash=" PADDRX
" pg_addr=" PADDRX "\n",
sdr, vsid, pgidx, hash, ctx->pg_addr[1]);
}
#endif
ret2 = find_pte(env, ctx, 1, rw, type);
if (ret2 != -1)
ret = ret2;
@ -1056,17 +1007,11 @@ static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
}
#endif
} else {
#if defined (DEBUG_MMU)
if (loglevel != 0)
fprintf(logfile, "No access allowed\n");
#endif
LOG_MMU("No access allowed\n");
ret = -3;
}
} else {
#if defined (DEBUG_MMU)
if (loglevel != 0)
fprintf(logfile, "direct store...\n");
#endif
LOG_MMU("direct store...\n");
/* Direct-store segment : absolutely *BUGGY* for now */
switch (type) {
case ACCESS_INT:
@ -1124,13 +1069,9 @@ static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
return -1;
}
mask = ~(tlb->size - 1);
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
LOG_SWTLB("%s: TLB %d address " ADDRX " PID %u <=> " ADDRX
" " ADDRX " %u\n",
__func__, i, address, pid, tlb->EPN, mask, (uint32_t)tlb->PID);
}
#endif
/* Check PID */
if (tlb->PID != 0 && tlb->PID != pid)
return -1;
@ -1223,12 +1164,8 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
continue;
zsel = (tlb->attr >> 4) & 0xF;
zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
LOG_SWTLB("%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",
__func__, i, zsel, zpr, rw, tlb->attr);
}
#endif
/* Check execute enable bit */
switch (zpr) {
case 0x2:
@ -1258,23 +1195,15 @@ static int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
}
if (ret >= 0) {
ctx->raddr = raddr;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: access granted " ADDRX " => " PADDRX
LOG_SWTLB("%s: access granted " ADDRX " => " PADDRX
" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
ret);
}
#endif
return 0;
}
}
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: access refused " ADDRX " => " PADDRX
LOG_SWTLB("%s: access refused " ADDRX " => " PADDRX
" %d %d\n", __func__, address, raddr, ctx->prot,
ret);
}
#endif
return ret;
}
@ -1500,10 +1429,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
mmu_idx, is_softmmu);
} else if (ret < 0) {
#if defined (DEBUG_MMU)
if (loglevel != 0)
cpu_dump_state(env, logfile, fprintf, 0);
#endif
LOG_MMU_STATE(env);
if (access_type == ACCESS_CODE) {
switch (ret) {
case -1:
@ -1753,30 +1679,19 @@ static always_inline void do_invalidate_BAT (CPUPPCState *env,
base = BATu & ~0x0001FFFF;
end = base + mask + 0x00020000;
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
LOG_BATS("Flush BAT from " ADDRX " to " ADDRX " (" ADDRX ")\n",
base, end, mask);
}
#endif
for (page = base; page != end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
#if defined (DEBUG_BATS)
if (loglevel != 0)
fprintf(logfile, "Flush done\n");
#endif
LOG_BATS("Flush done\n");
}
#endif
static always_inline void dump_store_bat (CPUPPCState *env, char ID,
int ul, int nr, target_ulong value)
{
#if defined (DEBUG_BATS)
if (loglevel != 0) {
fprintf(logfile, "Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
}
#endif
}
void ppc_store_ibatu (CPUPPCState *env, int nr, target_ulong value)
@ -2046,11 +1961,7 @@ void ppc_store_asr (CPUPPCState *env, target_ulong value)
void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
{
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "%s: " ADDRX "\n", __func__, value);
}
#endif
LOG_MMU("%s: " ADDRX "\n", __func__, value);
if (env->sdr1 != value) {
/* XXX: for PowerPC 64, should check that the HTABSIZE value
* is <= 28
@ -2062,12 +1973,8 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value)
void ppc_store_sr (CPUPPCState *env, int srnum, target_ulong value)
{
#if defined (DEBUG_MMU)
if (loglevel != 0) {
fprintf(logfile, "%s: reg=%d " ADDRX " " ADDRX "\n",
LOG_MMU("%s: reg=%d " ADDRX " " ADDRX "\n",
__func__, srnum, value, env->sr[srnum]);
}
#endif
if (env->sr[srnum] != value) {
env->sr[srnum] = value;
#if !defined(FLUSH_ALL_TLBS) && 0
@ -2205,23 +2112,15 @@ static always_inline void powerpc_excp (CPUState *env,
}
goto store_next;
case POWERPC_EXCP_DSI: /* Data storage exception */
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0) {
fprintf(logfile, "DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
LOG_EXCP("DSI exception: DSISR=" ADDRX" DAR=" ADDRX "\n",
env->spr[SPR_DSISR], env->spr[SPR_DAR]);
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
goto store_next;
case POWERPC_EXCP_ISI: /* Instruction storage exception */
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0) {
fprintf(logfile, "ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
LOG_EXCP("ISI exception: msr=" ADDRX ", nip=" ADDRX "\n",
msr, env->nip);
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@ -2244,11 +2143,7 @@ static always_inline void powerpc_excp (CPUState *env,
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0) {
fprintf(logfile, "Ignore floating point exception\n");
}
#endif
LOG_EXCP("Ignore floating point exception\n");
env->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
return;
@ -2262,12 +2157,8 @@ static always_inline void powerpc_excp (CPUState *env,
msr |= 0x00010000;
break;
case POWERPC_EXCP_INVAL:
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0) {
fprintf(logfile, "Invalid instruction at " ADDRX "\n",
LOG_EXCP("Invalid instruction at " ADDRX "\n",
env->nip);
}
#endif
new_msr &= ~((target_ulong)1 << MSR_RI);
if (lpes1 == 0)
new_msr |= (target_ulong)MSR_HVB;
@ -2327,17 +2218,11 @@ static always_inline void powerpc_excp (CPUState *env,
goto store_next;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
/* FIT on 4xx */
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0)
fprintf(logfile, "FIT exception\n");
#endif
LOG_EXCP("FIT exception\n");
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
goto store_next;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0)
fprintf(logfile, "WDT exception\n");
#endif
LOG_EXCP("WDT exception\n");
switch (excp_model) {
case POWERPC_EXCP_BOOKE:
srr0 = SPR_BOOKE_CSRR0;
@ -2458,10 +2343,7 @@ static always_inline void powerpc_excp (CPUState *env,
new_msr |= (target_ulong)MSR_HVB;
goto store_current;
case POWERPC_EXCP_PIT: /* Programmable interval timer interrupt */
#if defined (DEBUG_EXCEPTIONS)
if (loglevel != 0)
fprintf(logfile, "PIT exception\n");
#endif
LOG_EXCP("PIT exception\n");
new_msr &= ~((target_ulong)1 << MSR_RI); /* XXX: check this */
goto store_next;
case POWERPC_EXCP_IO: /* IO error exception */

64
target-ppc/op_helper.c
View File

@ -28,6 +28,16 @@
//#define DEBUG_EXCEPTIONS
//#define DEBUG_SOFTWARE_TLB
#ifdef DEBUG_SOFTWARE_TLB
# define LOG_SWTLB(...) do { \
if (loglevel) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_SWTLB(...) do { } while (0)
#endif
/*****************************************************************************/
/* Exceptions processing helpers */
@ -3564,13 +3574,9 @@ static void do_6xx_tlb (target_ulong new_EPN, int is_code)
EPN = env->spr[SPR_DMISS];
}
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@ -3596,13 +3602,9 @@ static void do_74xx_tlb (target_ulong new_EPN, int is_code)
CMP = env->spr[SPR_PTEHI];
EPN = env->spr[SPR_TLBMISS] & ~0x3;
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
LOG_SWTLB("%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
" PTE1 " ADDRX " way %d\n",
__func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
@ -3726,22 +3728,14 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
ppcemb_tlb_t *tlb;
target_ulong page, end;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
LOG_SWTLB("%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
LOG_SWTLB("%s: invalidate old TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@ -3766,26 +3760,18 @@ void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
tlb->attr = val & 0xFF;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
#endif
/* Invalidate new TLB (if valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
LOG_SWTLB("%s: invalidate TLB %d start " ADDRX
" end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
@ -3795,11 +3781,7 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
LOG_SWTLB("%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;
tlb->RPN = val & 0xFFFFFC00;
@ -3808,17 +3790,13 @@ void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
tlb->prot |= PAGE_EXEC;
if (val & 0x100)
tlb->prot |= PAGE_WRITE;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
LOG_SWTLB("%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
(int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
}
#endif
}
target_ulong helper_4xx_tlbsx (target_ulong address)
@ -3833,12 +3811,8 @@ void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
target_ulong EPN, RPN, size;
int do_flush_tlbs;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
LOG_SWTLB("%s word %d entry %d value " ADDRX "\n",
__func__, word, (int)entry, value);
}
#endif
do_flush_tlbs = 0;
entry &= 0x3F;
tlb = &env->tlb[entry].tlbe;

24
target-ppc/translate.c
View File

@ -42,6 +42,14 @@
//#define PPC_DEBUG_DISAS
//#define DO_PPC_STATISTICS
#ifdef PPC_DEBUG_DISAS
# define LOG_DISAS(...) do { \
if (loglevel & CPU_LOG_TB_IN_ASM) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_DISAS(...) do { } while (0)
#endif
/*****************************************************************************/
/* Code translation helpers */
@ -8232,13 +8240,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
gen_opc_icount[lj] = num_insns;
}
}
#if defined PPC_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "----------------\n");
fprintf(logfile, "nip=" ADDRX " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
}
#endif
LOG_DISAS("----------------\n");
LOG_DISAS("nip=" ADDRX " super=%d ir=%d\n",
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
if (unlikely(ctx.le_mode)) {
@ -8246,13 +8250,9 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
} else {
ctx.opcode = ldl_code(ctx.nip);
}
#if defined PPC_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "translate opcode %08x (%02x %02x %02x) (%s)\n",
LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), little_endian ? "little" : "big");
}
#endif
ctx.nip += 4;
table = env->opcodes;
num_insns++;

40
vl.c
View File

@ -154,6 +154,16 @@
//#define DEBUG_NET
//#define DEBUG_SLIRP
#ifdef DEBUG_IOPORT
# define LOG_IOPORT(...) do { \
if (loglevel & CPU_LOG_IOPORT) \
fprintf(logfile, ## __VA_ARGS__); \
} while (0)
#else
# define LOG_IOPORT(...) do { } while (0)
#endif
#ifdef TARGET_PPC
#define DEFAULT_RAM_SIZE 144
#else
@ -409,10 +419,7 @@ void isa_unassign_ioport(int start, int length)
void cpu_outb(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outb: %04x %02x\n", addr, val);
#endif
LOG_IOPORT("outb: %04x %02x\n", addr, val);
ioport_write(0, addr, val);
#ifdef USE_KQEMU
if (env)
@ -422,10 +429,7 @@ void cpu_outb(CPUState *env, int addr, int val)
void cpu_outw(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outw: %04x %04x\n", addr, val);
#endif
LOG_IOPORT("outw: %04x %04x\n", addr, val);
ioport_write(1, addr, val);
#ifdef USE_KQEMU
if (env)
@ -435,10 +439,7 @@ void cpu_outw(CPUState *env, int addr, int val)
void cpu_outl(CPUState *env, int addr, int val)
{
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "outl: %04x %08x\n", addr, val);
#endif
LOG_IOPORT("outl: %04x %08x\n", addr, val);
ioport_write(2, addr, val);
#ifdef USE_KQEMU
if (env)
@ -450,10 +451,7 @@ int cpu_inb(CPUState *env, int addr)
{
int val;
val = ioport_read(0, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inb : %04x %02x\n", addr, val);
#endif
LOG_IOPORT("inb : %04x %02x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();
@ -465,10 +463,7 @@ int cpu_inw(CPUState *env, int addr)
{
int val;
val = ioport_read(1, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inw : %04x %04x\n", addr, val);
#endif
LOG_IOPORT("inw : %04x %04x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();
@ -480,10 +475,7 @@ int cpu_inl(CPUState *env, int addr)
{
int val;
val = ioport_read(2, addr);
#ifdef DEBUG_IOPORT
if (loglevel & CPU_LOG_IOPORT)
fprintf(logfile, "inl : %04x %08x\n", addr, val);
#endif
LOG_IOPORT("inl : %04x %08x\n", addr, val);
#ifdef USE_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();